- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365372 > PT7A6632J (Pericom Semiconductor Corp.) PT7A6632 32-Channel HDLC Controller PDF資料下載
參數(shù)資料
| 型號： | PT7A6632J |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | PT7A6632 32-Channel HDLC Controller |
| 中文描述： | PT7A6632 32通道HDLC控制器 |
| 文件頁數(shù)： | 19/61頁 |
| 文件大?。?/td> | 379K |
| 代理商： | PT7A6632J |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁
Data Sheet
PT7A6632 32-Channel HDLC Controller
PT019(05/02)
Ver:2
19
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Memory Manager
The Memory Manager controls data flow between Transmit
Processor/Receive Processor and the external memory as shown
in Figure 18. CPU assigns the external memory into several
parts for activation information (Activation Memory) and data
processing information (Data Processing Memory) as shown
in Figure 20 in Section “External Memory Organization and
Definition”.
The Data Processing Memory is allocated to each transmit and
receive channel for data, command and status storage. The
CPU allocated enough memory in the buffers for the real-time
operation of transmit and receive with no data underrun or
overrun. The external memory is managed with minimal inter-
vention from the CPU.
The CPU sends out an ATTN signal to command PT7A6632 to
access the Activation Memory that contains channel number
and channel starting address. The SYSACC signal is asserted
by PT7A6632 during accessing the Activation Memory. After
the access, the ATACK will be asserted.
The Data Processing Memory contains such information as
next buffer address, operation mode, buffer size, data length,
buffer status and HDLC frame completion status. They are set
up by CPU. PT7A6632 accesses the buffers and processes data
and update the status in the buffers after processing. DMND is
asserted by the PT7A6632 to inform other devices using the
memory bus that PT7A6632 will access the external memory
one TCLK period after rising edge of the DMND. INTR as-
serted when PT7A6632 updates the status byte in buffers.
The memory manager responds to CPU-initiated changes in the
operational modes of a channel or relocation of the allocated
buffers without affecting the operation of the other channels.
The timing for the memory access is generated from SYSCLK.
From Rx Bit-Level Processor
/ To Tx Bit-Level Processors
Memory
Manager
A0-A15
D0-D7
READ
WRITE
AS
DMND
ATTN
ATACK, SYSACC, INTR
External
Memory
SYSCLK
CPU
PT7A6632
3
Figure 18. Diagram of Memory Manager with External Memory and CPU
State/Control Machine
The State/Control Machine processes the device mode and
status. MDFS sets the memory location pattern, i.e., the even
addresses in external memory are for higher bytes (MDFS = 1)
or for lower bytes (MDFS = 0) of the Next Buffer Starting Ad-
dress, Buffer Size and Data Length respectively.
Figure 19
UAEN sets the Upper address lines (A8 - A15) in high imped-
ance (UAEN = 1) or in Low state (UAEN = 0) when accessing
Activation Memory. When the upper address lines in high im-
pedance, the CPU can drive them to any state during accessing
activation memory.
HCS0, HCS1 and T1/CEPT select T1 or CEPT PCM-30 mode
and hyperchannel (Table 3). SIS selects trigger edge of RCLK
and TCLK. TSEREN sets TSER output line state, i.e., sending
data, sending “1” or in high impedance (Table 4).
CH0 to CH4 and Rx/Tx are status outputs indicating the cur-
rent active channel number and direction. CH0 is LSB, CH4 is
MSB.
The main clock for PT7A6632 is generated by the State/Con-
trol Machine from SYSCLK.
CH0-
CH4
Rx/Tx
RESET
HCS0-HCS1 T1/CEPT SIS
UAEN MDFS
State / Control Machine
5
2
To Rx and Tx Processors
& Memory Manager
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PT7C5022 | Crystal Oscillator Module ICs |
| PT7C5022AxATA | Crystal Oscillator Module ICs |
| PT7C5022AxATAE | Crystal Oscillator Module ICs |
| PT7C5022A5A | DIODE ZENER 150MW 36V 0603 |
| PT7C5022BxATA | Crystal Oscillator Module ICs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PT7A7511 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4.63V Reset Active Low Supervisor? |
| PT7A7512 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4.38V Reset Active Low Supervisor? |
| PT7A7513 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.08V Reset Active Low Supervisor? |
| PT7A7513WEX | 功能描述:IC SUPERVISOR 3.08V 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 其它有關(guān)文件:STM6905 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 類型:多壓監(jiān)控器 監(jiān)視電壓數(shù)目:5 輸出:開路漏極或開路集電極 復(fù)位:低有效 復(fù)位超時(shí):最小為 140 ms 電壓 - 閥值:2.188V，2.955V，可調(diào)，可調(diào)，可調(diào) 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:Digi-Reel® 產(chǎn)品目錄頁面:1197 (CN2011-ZH PDF) 其它名稱:497-8728-6 |
| PT7A7514 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.93V Reset Active Low Supervisor? |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。