參數(shù)資料
型號： PPC440SP-RNC667C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁數(shù)： 76/85頁
文件大小： 615K
代理商： PPC440SP-RNC667C
PowerPC 440SP Embedded Processor
76
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
DDR SDRAM I/O Specifications
The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the
same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note:
MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR
programming register. In a typical system, users advance MemClkOut by 90×. This depends on the specific
application and requires a thorough understanding of the memory system in general (refer to the DDR
SDRAM controller chapter in the
PPC440SP Embedded Processor User’s Manual
).
In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and
MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90
°
. Advancing MemClkOut0 by 90
°
creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to
MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.
The following DDR data is generated by means of
simulation
and includes logic, driver, package RLC, and lengths.
It is
not
to be used as a circuit design recommendation. Values are calculated over best case and worst case
processes with speed, temperature, and voltage as follows:
Best Case = Fast process, -40×C, +1.6V
Worst Case = Slow process, +85×C, +1.4V
Note:
In all the following DDR tables and timing diagrams,
minimum
values are measured under
best
case
conditions and
maximum
values are measured under
worst
case conditions.
The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.
Figure 7. DDR SDRAM Simulation Signal Termination Model
10pF
10pF
MemClkOut0
MemClkOut0
120W
50W
30pF
Addr/Ctrl/Data/DQS
V
TT
= SV
DD
/2
PPC440SP
Note:
This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is
not
a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
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