參數(shù)資料
型號(hào)： PPC440SP-RNC667C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁數(shù)： 61/85頁
文件大?。?/td> 615K
代理商： PPC440SP-RNC667C
PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
Data Sheet
AMCC Proprietary
61
System Interface
Halt
Halt from external debugger.
I
3.3V LVTTL
1, 4
GPIO00:17
General purpose I/O 0 through 17. To access these
functions, software must set DCR register bits.
I/O
3.3V LVTTL
GPIO18:29
General purpose I/O 18 through 29. To access these
functions, software must set DCR register bits.
I/O
3.3V PCI
GPIO30:31
General purpose I/O 30 through 31. To access these
functions, software must set DCR register bits.
I/O
3.3V LVTTL
SysClk
Main system clock input.
I
3.3V LVTTL
SysErr
Set to 1 when a machine check is generated.
O
3.3V LVTTL
SysPartSel
Not used.
I
na
3
SysReset
Main system reset. External logic can drive this
bidirectional pin low (minimum of 16 cycles) to initiate a
system reset. A system reset can also be initiated by
software.
I
3.3V LVTTL
1, 2
HISRRst
Hardware initiated self-refresh and system reset.
I
3.3V LVTTL
1, 2
ExtReset
External Reset. During the PPC440SP’s reset phase,
this signal is at down level.
O
3.3V LVTTL
TestEn
Test Enable.
I
3.3V LVTTL
3
TmrClk
Processor timer external input clock.
I
3.3V LVTTL
JTAG Interface
TCK
Test Clock.
I
3.3V LVTTL
1
TDI
Test Data In.
I
3.3V LVTTL w/pull-down
4
TDO
Test Data Out.
O
3.3V LVTTL
TMS
Test Mode Select.
I
3.3V LVTTL with pull-up
1
TRST
Test Reset. During chip power-up, this signal must be
low from the start of VDD ramp-up until at least 16
SysClk cycles after VDD is stable in order to initialize the
JTAG controller.
I
3.3V LVTTL with pull-up
5
Trace Interface
TrcClk
Trace data capture clock, runs at 1/4 the frequency of
the processor.
O
3.3V LVTTL
TrcBS0:2
Trace branch execution status.
O
3.3V LVTTL
TrcES0:4
Trace Execution Status is presented every fourth
processor clock cycle.
O
3.3V LVTTL
TrcTS0:6
Additional information on trace execution and branch
status.
O
3.3V LVTTL
Table 6. Signal Functional Description (Sheet 6 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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