參數(shù)資料
型號： PPC440SP-RNC667C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁數(shù)： 13/85頁
文件大?。?/td> 615K
代理商： PPC440SP-RNC667C
PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
Data Sheet
AMCC Proprietary
13
of the Memory Controller unit.
The RAID 5 and RAID 6 parity computations performed in the Memory Queue are assisted by the two-channel
DMA engine of the I2O/DMA controller unit, designated as DMA0 and DMA1. The RAID acceleration hardware
also provides various alternatives for balancing load and performance, depending on customer-specific application
firmware. The two-way crossbar bus architecture can perform data read and write operations simultaneously,
resulting in extremely high throughput.
RAID 6 capability is available only with the RAID-enabled part numbers (PPC440SP-RpCfffC) as indicated in the
ordering information section of this data sheet.
For more information about the RAID 6 implementation, description, and configuration of the acceleration
hardware, refer to the following AMCC documents:
PowerPC 440SP/440SPe RAID Support Application Note
PowerPC 440SP RAID Addendum to the User’s Manual
XOR/DMA2 Controller
The XOR/DMA2 controller performs the XOR functions needed to support RAID 5 applications including parity
generation and check functions used across data stripes in a RAID 5 system.
Features include:
Computes a bit-wise XOR on up to 16 data streams with result stored in designated target
Performs XOR check on up to 16 data streams
Driven by a linked list Command Block structure specifying control information, source operands, target
operand, status information, and link
Source and target streams may reside anywhere in PLB address space.
Provides completion status per Command Block to be handled by software at a later time
96-byte and 160-byte Command Block formats are supported
No memory alignment restrictions on operands or target
Internal register arrays and data buffers are parity protected
Can be used as a DMA controller (DMA2) with single source and target addresses
Serial Port
The serial port is compatible with the NS
16570 UART interface.
Features include:
One 8-pin, one 4-pin, and one 2-pin interfaces are provided
Selectable internal or external serial clock to allow wide range of baud rates
Register compatibility with 16750 register set
Complete status reporting capability
Fully programmable serial-interface characteristics
IIC Bus Interface
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