參數(shù)資料
型號(hào)： PPC440SP-RNC667C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 58/85頁(yè)
文件大?。?/td> 615K
代理商： PPC440SP-RNC667C
PowerPC 440SP Embedded Processor
58
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
DDR SDRAM Interface
BA0:2
Bank Address supporting up to eight internal banks.
O
2.5(1.8)V
DDR SDRAM
BankSel0:1
Selects up to two external DDR SDRAM banks.
O
2.5(1.8)V
DDR SDRAM
CAS
Column Address Strobe.
O
2.5(1.8)V
DDR SDRAM
ClkEn0:1
Clock Enable. One for each external bank.
O
2.5(1.8)V
DDR SDRAM
DM0:8
Memory write data byte lane masks. MEMDM8 is the
byte lane mask for the ECC byte lane.
O
2.5(1.8)V
DDR SDRAM
DQS0:8
DQS0:8
Byte lane data strobe. DQS8 is the data strobe for the
ECC byte lane. These signals are differential pairs.
I/O
2.5(1.8)V
DDR SDRAM
DIFF
ECC0:7
ECC check bits 0:7.
I/O
2.5(1.8)V
DDR SDRAM
MemAddr14:00
Memory address bus.
Note:
MemAddr14 is the most significant bit (msb).
O
2.5(1.8)V
DDR SDRAM
MemClkOut0:1
MemClkOut0:1
Subsystem clocks. These signals are differential pairs.
O
2.5(1.8)V
DDR SDRAM
DIFF
MemData63:00
Memory data bus.
Note:
MemData63 is the most significant bit (msb).
I/O
2.5(1.8)V
DDR SDRAM
MemDCFdbkD
Feedback driver, for I/O timing measurements.
O
2.5(1.8)V
DDR SDRAM
MemDCFdbkR
Feedback receiver. Connect externally to
MemDCFdbkD.
I
2.5(1.8)V
DDR SDRAM
MemODT0:1
Memory on-die termination control.
O
2.5(1.8)V
DDR SDRAM
MemVRef0
Memory reference voltage (SV
REF
) input.
I
2.5(1.8)V
DDR SDRAM Volt Ref
Rcv
MemVRef1
Memory reference voltage (SV
REF
) supplemental input.
I
2.5(1.8)V
DDR SDRAM Volt Ref
Sup
RAS
Row Address Strobe.
O
2.5(1.8)V
DDR SDRAM
WE
Write Enable.
O
2.5(1.8)V
DDR SDRAM
Table 6. Signal Functional Description (Sheet 3 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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