參數(shù)資料
型號： PPC440SP-RNC667C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁數(shù)： 56/85頁
文件大小： 615K
代理商： PPC440SP-RNC667C
PowerPC 440SP Embedded Processor
56
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
Table 6. Signal Functional Description (Sheet 1 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
PCI-X0:2 Interfaces
PCIX0:1Ack64/PCIX0:1ECC1
Ack64 or ECC1.
Normally used as Ack64 indicating that the target can
transfer data using 64 bits.
or
Used as ECC1 for PCI-X mode 2.
I/O
3.3V PCI or
1.5V PCI for mode 2
4
PCIX0:1AD63:00
PCIX2AD31:00
Address/Data bus (bidirectional) for PCI-X0 and PCI-X1.
Address/Data bus (bidirectional) for PCI-X 2.
I/O
3.3V PCI or
1.5V PCI for mode 2
PCIX0:1BE7:0
PCIX2BE3:0
PCI-X Byte Enables for PCI-X0 and PCI-X1
.
PCI-X Byte Enables for PCI-X2
.
I/O
3.3V PCI or
1.5V PCI for mode 2
PCIX0:1CalG0:1
PCIX2CalG0
External calibration resistor pads (G) for PCI-X0:2 (one
pad for each 32-bit bus group).
I
na
PCIX0:1CalR0:1
PCIX2CalR0
External calibration resistor pads (R) for PCIX0:2 (one
pad for each 32-bit bus group).
I
na
PCIX0:2Cap
Capable of PCI-X operation.
This analog input is sampled to configure PCI and
determine the state of the PCIX0:2VC output signal:
0.00V
DD
(0.0V) = Conventional PCI & PCIX0:2VC = 0
0.49V
DD
(1.6V) = PCI-X DDR 266 Mode 2 &
PCIX0:2VC = 1
0.75V
DD
(2.5V) = PCI-X 66 & PCIX0:2VC = 0
1.00V
DD
(3.3V) = PCI-X 133 & PCIX0:2VC = 0
I
na
PCIX0:2Clk
Provides timing to the PCI interface for PCI transactions.
Note:
If the PCI-X interface is not being used, drive this
pin with a 3.3V clock signal at a frequency
between 1 and 66MHz
I
3.3V PCI
PCIX0:2DevSel
Indicates the driving device has decoded its address as
the target of the current access.
I/O
3.3V PCI
4
PCIX0:2ECC5:2
PCIX2ECC1
PCIX2ECC6
ECC check bits 5–2. All ECC bits are valid only for PCIX
DDR mode 2.
Note:
See PCIX0:2Par for ECC0.
See PCIX0:1Ack64 for ECC1.
See PCIX0:1Req64 for ECC6.
See PCIX0:1Par64 for ECC7.
I/O
3.3V PCI or
1.5V PCI for mode 2
PCIX0:2Frame
Driven by the current master to indicate beginning and
duration of an access.
I/O
3.3V PCI
4
PCIX0:2Gnt0:1
PCIX0:1Gnt2:3
Indicates that the specified agent is granted access to
the bus. When using an external PCI/PCI-X arbiter,
connect the external arbiter's Grant line to this signal.
I/O
3.3V PCI
4
PCIX0:2IDSel
Used as a chip select during configuration read and
write transactions.
I
3.3V PCI
5
PCIX0:2INTA
Level sensitive PCI interrupt.
O
3.3V PCI
PCIX0:2IRDY
Indicates initiating agent’s ability to complete the current
data phase of the transaction.
I/O
3.3V PCI
4
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