參數(shù)資料
型號(hào)： PPC440SP-RNC667C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁數(shù)： 5/85頁
文件大?。?/td> 615K
代理商： PPC440SP-RNC667C
PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
Data Sheet
AMCC Proprietary
5
PPC440SP Functional Block Diagram
Figure 2. PPC440SP Functional Block Diagram
The PPC440SP is a System on a chip, which uses IBM
CoreConnect
Bus Architecture.
Implemented with the Crossbar option, the IBM CoreConnect buses provide:
128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data
paths (10.6GB/sec total)
32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various processor accessible address regions. The second address
map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the
PPC440SP processor through the use of
mtdcr
and
mfdcr
instructions.
UART2
UART1
IIC1
Processor Core
DCR Bus
32KB
I-Cache
On-chip Peripheral Bus (OPB)
GPIO
Accelerator
Unit
(DMA2)
Bridge
DDR2 SDRAM
Controller
External
Bus Controller
(EBC)
Clock,
Control,
Reset
Power
Mgmt
JTAG
Timers
MMU
OPB
Interrupt
Controller
Universal
32KB
D-Cache
XOR/DMA
PPC440
DDR PCI-X
PCI1
MAL
Ethernet
10/100/
1000
(EMAC)
DCRs
GPT
L2 Cache/SRAM
Low Latency (LL) Segment
High Bandwidth (HB) Segment
Controller
(DMA0 and
DMA1)
Processor Local Bus (PLB)
Trace
Arbiter
PLB
I2O/DMA
Host
64 bits
Local
64 bits
Local
32 bits
Memory
Queue
PCI0
PCI2
MII,
GMII
IIC0
UART0
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