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| 型號： | PPC440SP-RNC667C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerPC 440SP Embedded Processor |
| 中文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 12/85頁 |
| 文件大小： | 615K |
| 代理商： | PPC440SP-RNC667C |
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PowerPC 440SP Embedded Processor
12
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
24-bit address, 16MB address space
Peripheral Device pacing with external “Ready”
Latch data on Ready, synchronous or asynchronous
Programmable access timing per device
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
Programmable address mapping
Ethernet Controller Interface
The Ethernet support interfaces to the physical layer, but the PHY is not included on the chip.
Features include:
One 10/100/1000 interface running in full- and half-duplex modes
– One full Media Independent Interface (MII) with 4-bit parallel data transfer
– One Gigabit Media Independent Interface (GMII)
I2O/DMA Controller
The I20/DMA controller provides support for I20 messaging and two DMA controllers (DMA0 and DMA1). I2O
manages message frame address (MFA) FIFOs or queues in memory in response to I2O register reads and writes
and transfers message frames. The DMAs provide normal memory access support to ease the CPU burden.
I2O features include:
I2O pull- and push-messaging methods
Dynamic message frame size
Programmable FIFO size (4096 64-bit MFAs maximum)
64-bit and 32-bit MFA sizes
Three interrupt gathering methods
Registered MFA prefetch and posting
32-bit inbound and outbound doorbell registers
Four 32-bit scratch pad registers
DMA features include:
Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)
512-byte/1KB buffering for DMA0/DMA1
Simultaneous fill and drain (PLB read/write pipelining)
Any source PLB address to any destination address
No memory alignment restrictions on source or destination
32-byte command descriptor block
Maximum transfer size of 16MB
64-bit addressing
Prefetch indicators for PCI-X buffer management (DMA1 only)
Optional RAID 5 and RAID 6 Acceleration Hardware
The 440SP provides integrated acceleration hardware that implements high throughput RAID 5 and RAID 6
algorithms to compute the single parity P for RAID 5, and dual parity P & Q for RAID 6. RAID 5 is used to recover
data in the case of a single disk drive failure, and RAID 6 provides for data recovery if two disk drives fail.
The 440SP offers a choice of two XOR engines for computing the P parity. The first choice is available with the
XOR/DMA2 acceleration unit and is used for RAID 5. The second choice for XOR parity computation, along with
the RAID 6 Galois Field GF(2
8
)-based polynomial computations, resides inside the Memory Queue functional block
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