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| 型號(hào)： | PM8621 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | NSE-8G⑩ Standard Product Data Sheet Preliminary |
| 中文描述： | 網(wǎng)絡(luò)搜索引擎，第八代⑩標(biāo)準(zhǔn)的產(chǎn)品數(shù)據(jù)的初步 |
| 文件頁(yè)數(shù)： | 43/184頁(yè) |
| 文件大?。?/td> | 1122K |
| 代理商： | PM8621 |
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NSE-8G Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
42
9.1.4
Data Recovery Unit (DRU)
The DRU is a fully integrated data recovery and serial to parallel converter that can be used for
777.6 Mbit/s NRZ data. 8B/10B block code is used to guarantee transition density for optimal
performance.
The DRU recovers data and outputs a ten-bit word synchronized with a line rate divided by ten,
gated clock to allow frequency deviations between the data source and the local oscillator. The
output clock is not a recovered clock. The DRU accumulates 10 data bits and outputs them on the
next clock edge. If 10-bits are not available for transfer at a given clock cycle, the output clock is
gated.
The DRU provides moderate high frequency jitter tolerance suitable for inter-chip serial link
applications. It can support frequency deviations up to
±
100 ppm.
There are 12 instances of the DRU on the NSE-8G.
9.1.5
Parallel to Serial Converter (PISO)
The PISO is a parallel-to-serial converter designed for high-speed transmit operation, supporting
up to 777.6 Mbit/s.
There are 12 instances of the PISO on the NSE-8G.
9.1.6
Clock Synthesis Unit (CSU)
The CSU is a fully integrated clock synthesis unit. It generates low jitter multi-phase differential
clocks at 777.6 MHz for the use by the transmitter.
There is one instance of the CSU on the NSE-8G.
9.2
Receive 8B/10B Frame Aligner (R8TD)
The Receive 8B/10B serial SBI336S Bus frame aligner, R8TD, frames to the receive stream to
find 8B/10B character boundaries. It also contains a FIFO to bridge between the timing domain of
the receive LVDS links and the system clock timing domain. The R8TD blocks perform framing
and elastic store functions on data retrieved from the receive LVDS links, RP[x]/RN[x].
9.2.1
FIFO Buffer
The FIFO buffer sub-block provides isolation between the timing domains of the associated
receive LVDS link and that of the system clock, SYSCLK. Data with arbitrary alignment to the
8B/10B characters, are written into a 10-bit by 24-word deep FIFO at the link clock rate. Data is
read from the FIFO at every SYSCLK cycle.
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