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| 型號： | PM8621 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | NSE-8G⑩ Standard Product Data Sheet Preliminary |
| 中文描述： | 網(wǎng)絡搜索引擎，第八代⑩標準的產(chǎn)品數(shù)據(jù)的初步 |
| 文件頁數(shù)： | 158/184頁 |
| 文件大小： | 1122K |
| 代理商： | PM8621 |
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NSE-8G Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
157
12.13.2 Nave Algorithm
We begin by describing a simplified version of the algorithm, applied to a specific SBS/NSE-8G
configuration. Four SBS devices are connected by one port each to an NSE, which is likewise
connected by one port to the egress side of each SBS device. Only four ingress/egress ports on the
NSE-8G are in use in this application, but the ideas generalize easily to larger fabrics.
Information flows from left to right. Each edge connects an egress port (on the left) to an ingress
port (on the right); each such edge has a capacity of 9720 timeslots.
For present purposes, we consider the SBSs to be supporting a single P-SBI port (eight bits at
77.76 MHz, or STS-12). Also, we ignore the “standby” LVDS port. This reduces the SBS from a
multi-ported Memory switch (which it in fact is) to a simpler two-ported (P-SBI and Active S-
SBI) Time switch. This reduction in complexity makes the following discussion more
straightforward, but does not reduce the algorithm’s ability to deal with the more complex cases
introduced by the use of the four slower P-SBI ports, or by concurrent use of the standby LVDS
port. The nature of switching in this application is illustrated by Figure 19. The two dimensional
4-X-4 matrices represent octet slots in both space (vertical) and time (horizontal). We trace
through the switching processing in the following steps:
Matrix I represents the arrival of the 16 octets from the SBI load devices.
The mapping from Matrix I to Matrix II represents the Time switching action of all four ingress
SBSs. Each SBS carries out an arbitrary permutation (including 1-to-many) of the ingress Time
slots within each Space row.
The mapping from Matrix II to mat Matrix rix III represents the Space switching action of the
NSE. During each Time slot, the NSE-8G carries out an arbitrary permutation (including 1-to-
many) of the ingress Space slots.
The mapping from Matrix III to Matrix IV represents the Time switching action of all four egress
SBSs. Each SBS carries out an arbitrary permutation (including 1-to-many) of the ingress Time
slots within each Space row.
It is known that any complete permutation from Matrix I to Matrix IV can be carried out in this
way. Figure 19 illustrates two particular octets (
α
and
β
) being switched through the SBS-NSE-
SBS Time:Space:Time switch.
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