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PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
92
9
MICROPROCESSOR PORTS
9.1
Microprocessor Ports Summary
NOTES:
All read/write port bits marked “Not used” must be written with the value 0 to maintain software com-
patibility with future versions.
All port bits marked “Reserved” should not be written. Software modifications to these locations after
setup may cause incorrect operation.
For 16-bit registers at addresses
X
and (
X
+1), bit 15 is address
X
bit 7 and bit 0 is address (
X
+1) bit 0.
For 32-bit registers at addresses
X
to (
X
+3), bit 31 is address
X
bit 7 and bit 0 is address (
X
+3) bit 0. For
example, the INPUT_PORT_ENABLE register.
For 128-bit registers at addresses
X
to (
X
+F
h
), nibble 31 is address
X
bits 7 to 4 and nibble 0 is address
(
X
+F
h
) bits 3 to 0. For example, the INPUT_MARKED_CELLS_COUNT register.
Registers marked with a “
t
” should only be modified while the chip is in software reset.
Table 31. Microprocessor Ports Summary
Address
(in Hex)
Name
Read or Write
Description
Chip Control/Status Registers
0
REVISION
R
Contains the device revision number (namely,
01
h
).
1
CHIP_MODE
R/Wt
Assorted chip-configuration bits.
2-3
MULTICAST_GROUP_INDEX
R/W
Multicast group to be modified or read.
4-7
MULTICAST_GROUP_VECTOR
R/W
Set of destinations comprising the multicast group.
8
MULTICAST_GROUP_OP
R/W
Operation to be performed.
9-A
UC/MC_FAIRNESS_REGISTER
R/W
Unicast/Multicast behavior for cells of the same
priority.
B
EXTENDED_CHIP_MODE
R/Wt
Extended chip mode
C
MULTICAST_GROUP_INDEX_MSB
R/W
Highest byte of Multicast group to be modified or read.
D-F
RESERVED
—
Port Control/Status Registers
10-13
INPUT_PORT_ENABLE
R/W
Enable input ports and associated interrupts.
14-17
OUTPUT_PORT_ENABLE
R/W
Enable output ports and associated interrupts.
18-27
INPUT_MARKED_CELLS_COUNT
R
Count of marked cells arriving at inputs.
28-37
OUTPUT_MARKED_CELLS_COUNT
R
Count of marked cells leaving at outputs.
38-3B
PARITY_ERROR_PRESENT
R
Parity error status on inputs during the last cell time.
PARITY_ERROR_LATCH
R
Indicates if any parity errors have occurred since the
last read.
40-43
PARITY_ERROR_INT_MASK
R/W
Enables/disables interrupt due to parity error.