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參數(shù)資料
| 型號(hào)： | PM7349 |
| 廠(chǎng)商： | PMC-SIERRA INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, 1.45 MM HEIGHT, SBGA-256 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 56K |
| 代理商： | PM7349 |
PM7349
PMC-Sierra,Inc.
Quad J2, E3 and DS-3 Framer
S/UNI
-4xD3F
PMC-2000369 (R2)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS
’
INTERNAL USE
Copyright PMC-Sierra, Inc. 2000
FEATURES
Quad DS-3, E3 (G.751 and G.832),
and J2 framers.
Each channel can be independently
configured to be a DS-3, E3, or J2
Framer.
Gapped transmit and receive clocks
can be optionally generated for
interface to devices which only need
access to payload data bits.
Provides programmable pseudo-
random test pattern generation,
detection, and analysis features.
Provides integral transmit and receive
HDLC controllers with 128-byte FIFO
depths.
Provides performance monitoring
counters suitable for accumulation
periods of up to 1 second.
Provides an 8-bit microprocessor
interface for configuration, control and
status monitoring.
Provides a standard five signal
P1149.1 JTAG test port for boundary
scan board test purposes.
Low power 3.3 V CMOS technology
with 5 V tolerant inputs.
Available in a high density 256-pin
SBGA package (27 mm x 27 mm).
RECEIVER SECTION
Provides frame synchronization for the
M23 or C-bit parity DS3 applications,
alarm detection, and accumulates line
code violations, framing errors, parity
errors, path parity errors and FEBE
events. In addition, far end alarm
channel codes are detected, and an
integral HDLC receiver is provided to
terminate the path maintenance data
link.
Provides frame synchronization for the
G.751 or G.832 E3 applications, alarm
detection, and accumulates line code
violations, framing errors, parity errors,
and FEBE events. In addition, in
G.832, the Trail Trace is detected, and
an integral HDLC receiver is provided
to terminate either the Network
Requirement or the General Purpose
data link.
Provides frame synchronization for
G.704 and NTT 6.312 Mbit/s J2
applications, alarm detection, and
accumulates line code violations,
framing errors, and CRC parity errors.
An integral HDLC receiver is provided
to terminate the data link.
Provides a receive HDLC controller
with a 128-byte FIFO to accumulate
data link information.
Provides detection of yellow alarm and
loss of frame (LOF), and accumulates
BIP-8 errors, framing errors and FEBE
events.
Provides programmable pseudo-
random test-sequence detection (up to
232-1 bit length patterns conforming to
ITU-T O.151 standards) and analysis
features.
TRANSMITTER SECTION
Provides frame insertion for the M23 or
C-bit parity DS3 applications, alarm
T
T
T
T
T
T
R
R
R
RBOC
Rx
FEAC
RDLC
Rx
HDLC
PMON
Perf.
Monitor
Rx
O/H
Access
1/2 TTB
Tx Trail
Buffer
Tx
O/H
Access
TDPR
Tx
HDLC
XBOC
Tx
FEAC
TRAN
J2, E3, or DS3
Transmit Framer
Line
Encode
FRMR
J2, E3, or DS3
Receive Framer
Line
Decode
1/2 TTB
Rx Trail
Buffer
R
R
F
R
R
R
P
TCLK[4:1]
TPOS/TDATO[4:1]
TNEG/TOHM[4:1]
RCLK[4:1]
RPOS/RDATI[4:1]
RNEG/RLCV[4:1]
T
T
T
T
T
T
T
T
IEEE P1149.1
JTAG Test
Access Port
Microprocessor
I/F
A
A
C
W
R
R
D
I
BLOCK DIAGRAM
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