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參數(shù)資料
| 型號(hào)： | PM73488 |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 5 Gbit/s ATM Switch Fabric Element |
| 中文描述： | ATM SWITCHING CIRCUIT, PBGA596 |
| 封裝： | EPBGA-596 |
| 文件頁數(shù)： | 26/135頁 |
| 文件大?。?/td> | 1735K |
| 代理商： | PM73488 |
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PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
28
2.4.1
Multicast Queue Engine
The multicast queue engine associates input ports with cell buffers, computes backpressure for the input ports, and
stores incoming cells into the buffers. In doing so, it guarantees:
No input port will have more than three cells pending in the QSE — this can be changed to allow four
pending cells by setting the “Allow 4 Bits Per Port” bit (bit 1) in the BP CONTROL register.
No input port will have more than two high-priority cells pending.
The sum of low- and medium-priority cells pending from any single input port will be less than 2.
In addition, the queue engine allows buffers to be reserved for high-priority cells or high/medium-priority cells. This
is
controlled
by
bits
2
and
3
of
the
BP_CONTROL_REGISTER
“BP_CONTROL_REGISTER” on page 109
). The four possible combinations for these two bits are listed in Table 1.
The multicast queue engine will compute backpressure for the preceding QSE/QRT to ensure the constraints listed in
Table 1 are satisfied. The same reservation policy applies to
both
sets of 32 buffers.
(refer
to
section
9.3.29
After the MGV address for the cell enters the QSE, the MGV associated with that cell is fetched and loaded into the
QUEUE_COMPLETION_REGISTER (an internal register) as soon as possible.
2.4.2
Multicast Dequeue Engine
In each cell time, the multicast dequeue engine selects one multicast cell for each of the 32 output ports. In effect, all
multicast cells wanting to go to a particular output port arbitrate among themselves to select the most appropriate
port. Arbitration occurs independently for all 32 ports. The cells winning the internal multicast arbitration then com-
pete with the incoming unicast cells for access to the output ports. Multicast arbitration winners are chosen to satisfy
the following conditions in this sequence:
Obey backpressure from the down stream QSE or QRT. Only cells with the allowed priorities will take part
in arbitration.
Higher priority cells win over lower priority cells.
Cells that came in earlier win over cells that came in later (if they have the same priority).
If multiple cells have the same priority and came in simultaneously, cells from a random input gang group
will be selected.
If multiple cells have the same priority, came in simultaneously, and belong to the same input gang group,
the cell with the lowest port number will be selected.
Ties are broken randomly.
Table 1. BP_CONTROL_REGISTER; Threshold Control Bits for Each Set of 32 Buffers
Bit 3
Bit 2
Description
0
0
Four buffers are reserved for high-priority cells.
Four buffers are reserved for high- or medium-priority cells.
All other buffers can be used by any cell.
0
1
Four buffers are reserved for high-priority cells.
All other buffers can be used by any cell.
1
0
Eight buffers are reserved for high- or medium-priority cells.
All other buffers can be used by any cell.
1
1
All buffers can be used by any cell.
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