
PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
14
guaranteed "Quality of Service (QOS)" requirements. The recommended QSE fabric configurations for high quality
switching takes these results into account; for example the 3 stage 160 Gb/s sustained throughput fabric has a peak
capacity of 256 Gb/s (60% margin).
The QSE fabric is store-and-forward for multicast traffic. Cell replication is performed in an optimal tree based
manner where replication is done as far downstream as possible and each QSE contains cell buffers to buffer
multicast cells. A multipriority backpressure feedback is used to control the flow of multicast cells through the fabric.
FEATURES
Switching Algorithm
Supports blocking resolution in the switch fabric.
Guarantees a lower bound on switch performance using a patented randomization algorithm called Evil
Twin Switching.
Determines routes using specified bits in the header (self-routing switch fabric) for unicast traffic.
Determines output groupings using a lookup table for multicast traffic.
Allows output ports to be combined in groups of 1, 2, 4, 8, 16, or 32 for unicast traffic.
Allows output ports to be combined in groups of 1, 2, or 4 for multicast traffic.
Multicast Support
Supports optimal tree-based multicast replication in the switch fabric.
Supports 512 internal multicast groups, expandable to 256K with external SRAM.
Provides 64 internal cell buffers for multicast cells.
Diagnostic/Robustness Features
Checks the header parity.
Counts tagged cells.
Checks for connectivity and stuck-at faults on all switch fabric interconnects.
I/O Features
Provides 32 switch fabric interfaces with integrated phase aligner clock recovery circuitry.
Provides a Start-Of-Cell (SOC) output per four switch element interfaces.
Provides an external 8-bit Synchronous SRAM (SSRAM) interface for multicast group expansion.
Provides a demultiplexed address/data CPU interface.
Provides an IEEE 1149.1 (JTAG) boundary scan test bus.
Physical Characteristics
3.3 V supply voltage.
5 V tolerant inputs.
596-pin Enhanced Plastic Ball Grid Array (EPBGA) package.
Operates from a single 66 MHz clock.