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參數(shù)資料
| 型號： | PM73488 |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 5 Gbit/s ATM Switch Fabric Element |
| 中文描述： | ATM SWITCHING CIRCUIT, PBGA596 |
| 封裝： | EPBGA-596 |
| 文件頁數(shù)： | 45/135頁 |
| 文件大小： | 1735K |
| 代理商： | PM73488 |
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PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
47
4
QSE FEATURE DESCRIPTIONS
4.1
The QSE has an algorithm that allows unicast cells to take advantage of multiple paths in multistage switch fabrics.
This algorithm is run simultaneously by all QSEs in a system. Since the position (row and column) of each QSE is
known (refer to
section 9.3.26 “SWITCH_FABRIC_ROW” on page 107
and to
section 9.3.27
“SWITCH_FABRIC_COLUMN” on page 108
), and they all receive a synchronizing strobe (CELL_24_START),
each QSE can determine exactly what the other QSEs are doing. This enables the QSEs to act globally to minimize
cell congestion in the switch fabric.
Distribution Algorithm
4.2
Each QSE needs to be informed when the window occurs during which the SE_SOC_IN is valid for the input ports.
Generally, since this window can vary from one QSE to another in the fabric, it is made software programmable by
setting the CELL_START_OFFSET register (refer to
section 9.3.28 “CELL_START_OFFSET” on page 109
). The
significance of this register is as follows: The QSE generates an internal signal called "Local CELL_START", which
is simply a delayed version of external CELL_START input, where the delay is the number of clock cycles given in
the CELL_START_OFFSET register. The valid window for accepting SE_SOC_IN is the 8-clock-cycle interval
immediately preceding the pulse of local CELL_START signal. (For a detailed timing diagram, see “Relation
Between External CELL_START and Local CELL_START” on page 47.)
Cell Start Offset Logic
4.2.1
Relation Between External CELL_START and Local CELL_START
Figure 30 shows the relationship between the external CELL_START signal and the local CELL_START signal,
which is used internally by the QSE. The signal offset is programmable through the microprocessor interface (refer to
section 9.3.28 “CELL_START_OFFSET” on page 109
) to allow for easy system synchronization.
The QSE performs cut-through routing wherever possible and requires the SOC to be synchronized across all input
ports. For greater flexibility, the QSE allows cells starting within a window of eight clock pulses to be considered
valid. The end of the 8-clock-cycle window is also indicated by the local CELL_START signal.
Figure 30. QSE Cell-Level Timing
SOC Pulses Derived from the SE_SOC_IN Signals
Tseau
Tesu
CSTART Delay
CST High
8 Clock Cycles
Valid SOC Pulses
Clock Cycle
Delta
Delta
CST Low
SE_CLK
External CELL_START
Local CELL_START
SOC Pulses
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