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PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
58
Pin Name
Type
Pin No.
Function
RSCLK[31]
RSCLK[30]
RSCLK[29]
RSCLK[28]
RSCLK[27]
RSCLK[26]
RSCLK[25]
RSCLK[24]
RSCLK[23]
RSCLK[22]
RSCLK[21]
RSCLK[20]
RSCLK[19]
RSCLK[18]
RSCLK[17]
RSCLK[16]
RSCLK[15]
RSCLK[14]
RSCLK[13]
RSCLK[12]
RSCLK[11]
RSCLK[10]
RSCLK[9]
RSCLK[8]
RSCLK[7]
RSCLK[6]
RSCLK[5]
RSCLK[4]
RSCLK[3]
RSCLK[2]
RSCLK[1]
RSCLK[0]
Input
AC25
AD26
AD25
AE26
AC22
AF23
AE23
AD21
AC21
AE21
AD8
AF8
AD6
AC6
AD1
AC3
AE7
AF6
AD5
AC5
AD4
AE4
AD2
AB3
AB1
AB2
Y3
AA1
Y2
V3
W1
W2
The
Receive Serial Clock
(RSCLK[31:0]) signals
contain the recovered line clock for the 32
independently timed links. The RSDATA[31:0]
signals are sampled on the rising edge of the
corresponding RSCLK[31:0] clock.
For channelized T1 or E1 links, RSCLK[n] must
be gapped during the framing bit (for T1
interfaces) or during time-slot 0 (for E1
interfaces) of the RSDATA[n] stream. The S/UNI-
IMA-84 uses the gapping information to
determine the time-slot alignment in the receive
stream. RSCLK[31:0] is nominally a 50% duty
cycle clock of 1.544 MHz for T1 links and 2.048
MHz for E1 links.
For unchannelized links, RSCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e., not part of the ATM cell).
The RSCLK[31:0] input signal is nominally a 50%
duty cycle clock of 1.544 MHz for T1 links and
2.048 MHz for E1 links.
The RSCLK[31:0] may operate at higher rates in
the unchannelized mode. At higher rates, the
amount of lines available is limited See 12.3.2.2
for more details.