![](http://datasheet.mmic.net.cn/330000/PM7341_datasheet_16444387/PM7341_136.png)
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
138
RDAT_INTR
When set, there is an interrupt pending from the RDAT block. Read the
RDAT_INTR_STATUS_REG located in register 0x310 to determine the cause
of the interrupt. This bit indicates current status and will clear only when no
interrupt conditions remain in RDAT_INTR_STATUS_REG. On read:
0) No interrupt pending from the RDAT block.
1) Interrupt pending from the RDAT block.
ICP_CELL_AVL
When set, it indicates that a new ICP Cell is available in the ICP cell buffer.
The ICP cell buffer can be used to extract ICP cells for a group. This bit is
cleared when register 0x230 ICP Cell Forwarding Status is read.
0) No ICP cell is available.
1) An ICP cell is available in the ICP buffer.
SBI_ADD_INTR
When set, it indicates that an interrupt is pending related to the SBI-Add Bus
(also known as the Insert SBI bus). Read the Insert Master Interrupt Status
Register (Register “0x0E4”) to find the cause of the interrupt. This bit indicates
current status and will clear only when no interrupt conditions remain in the
Insert Master Interrupt Status Register. On read:
0) No SBI Add Bus interrupt pending.
1) SBI Add Bus interrupt is pending.
SBI_DROP_INTR
When set, it indicates that an interrupt is pending related to the SBI-Drop Bus,
also known as the Extract SBI bus. Read the Extract Master Interrupt Status
Register (Register 0x0BE) to find the cause of the interrupt. This bit indicates
current status and will clear only when no interrupt conditions remain in the
Extract Master Interrupt Status Register. On read:
0) No SBI Drop Bus interrupt pending
1) SBI Drop Bus interrupt is pending
SBI_ALARM
When set, it indicates that an interrupt is pending in one of the 0x084-0x08E:
SBI Extract Alarm Interrupt Registers located at 0x084-0x08E. registers. This
bit indicates current status, and will clear only when no interrupt conditions
exist in either SBI alarm registers. On read:
0) No SBI alarm pending
1) SBI alarm pending