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PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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change or an error occurred on an IMA group. The RIPP Interrupt status FIFO
contains the groups that have enabled conditions active. The RIPP Interrupt
status FIFO is managed so that each group will only ever have a single entry in
the FIFO. To facilitate interrupt processing, a RIPP command is provided to
gather all interrupts and status for a group and all of the links within the group in
one snapshot.
TIMA_INTR provides information that a link FIFO has overflowed. During normal
operations, this will only happen when: (1) the TIMA is misconfigured or (2) the
rate difference between the clocks in an IMA group is greater than the maximum
tolerance. To determine which link has experienced a problem, the TIMA Link
FIFO Overflow Status registers should be read.
RDAT_INTR indicates either: (1) that cells were dropped due to Any-
PHY/UTOPIA congestion or (2) that TC group cells were dropped due to FIFO
overflow. To determine the cause of the interrupt, the RDAT Master Interrupt
register should be read.
ICP_CELL_AVL indicates that an ICP cell is available in the ICP cell buffer. To
enable diagnostics, the capability to forward a group’s ICP cells to the
microprocessor is provided. When a cell is forwarded to the microprocessor, it is
placed in the ICP cell buffer and the interrupt is triggered. As new ICP cells
arrive, they overwrite the ICP cell buffer unless the buffer is locked for reading.
Once the ICP cell buffer is locked, further ICP cells will not be forwarded until the
ICP cell buffer is unlocked. This trace can be enabled on a per-group basis.
10.6.2.4
Miscellaneous Interrupts
MISC_INTR indicates that an interrupt condition exists in the Miscellaneous
Interrupt register. These bits are read-and-clear and usually indicate that
transitory conditions have occurred, such as parity errors, SDRAM CRC errors,
interrupt FIFO overflows, and UTOPIA L2 interface errors.
10.6.3 Registers
The Register Memory Map in Table 4 shows where the normal mode registers
are accessed. The resulting register organization is split into sections: Master
configuration registers, TC Layer, SBI Interface, Clock/Data Interface and IMA
Sublayer registers.
On power up, the S/UNI-IMA-84 requires configuration. For proper operation,
register configuration is necessary in order to program addresses for the Any-