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PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
383
Figure 27 shows three DS-3 tributaries mapped onto the SBI bus. A negative
justification is shown for DS-3 #2 during the H3 octet with DPL asserted high. A
positive justification is shown for DS-3#1 during the first DS-3#1 octet after H3
(which has DPL asserted low).
13.2 SBI ADD Bus Interface Timing
The SBI ADD bus functional timing for the transfer of tributaries - whether T1/E1
or DS3 - is the same as for the SBI DROP bus. The only difference is that the
SBI ADD bus has a few additional signals. The AJUST_REQ signal is used to by
the TEMUX-84 in SBI master timing mode to provide transmit timing to SBI link
layer devices. The AACTIVE signal is asserted whenever the S/UNI-IMA-84 is
driving the SBI ADD bus and is used with the ADETECT signals of other Link
devices to detect and protect against SBI ADD bus conflicts.
Figure 28
- SBI ADD Bus Adjustment Request Functional Timing
C1
H3
H3
H3
DS-3 #1 DS-3 #2DS-3 #3DS-3 #1
REFCLK
C1FP
ADATA[7:0]
APL
AV5
ADP
AJUST_REQ
AACTIVE
Figure 28 illustrates the operation of the SBI ADD Bus, using positive and
negative justification requests as an example. (The responses to the justification
requests would take effect during the next multi-frame.) The negative justification
request occurs on the DS-3#3 tributary when AJUST_REQ is asserted high
during the H3 octet. The positive justification occurs on the DS-3#2 tributary
when AJUST_REQ is asserted high during the first DS-3#2 octet after the H3
octet. The AACTIVE signal is shown for the case in which S/UNI-IMA-84 is
driving DS-3#2 onto the SBI ADD bus.