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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
390
13 Operations
13.1
Configuring the Scalable Data Queue
The SDQ supports a number of FIFO sizes, from 128 bytes (equal to 2 ATM cells) to 12,288
bytes (equal to 192 ATM cells). The 12,288-byte total storage can be carved up into a maximum
of 48 FIFOs.
In order to configure the SDQ-ATLAS, the user first determines the size of each FIFO in blocks
(1 block = 128 bytes) based on the PHYs in the system, and adds them all up. The total number of
blocks should be less than or equal to 96. The user then needs to program four things for a given
PHY:
FIFO pointer – this is the starting block number, which is an integer from 0 to 95. Since there are
96 blocks in total, this is a 7-bit number, as specified in the FIFO indirect configuration register
(FIFO_PTR[6:0] field). There is no restriction on where a PHY’s FIFO may start, so long as no
FIFOs overlap.
FIFO size – this is the size of a FIFO measured in blocks. Refer to the Suggested FIFO size
encoding table below for the values used to specify the FIFO sizes, and a guide to sizing the FIFO
based on the bandwidth of the associated PHY. It is up to the discretion of the user to apply this
guide to each specific case. Room permitting, it is always acceptable to increase the amount of
space for a FIFO. This number is specified in the FIFO indirect configuration register
(FIFO_SIZE[6:0] field). Packets occupy a number of bytes equal to their length, rounded up to
the next multiple of 4 bytes; ATM cells occupy 64 bytes apiece, regardless of prepends or
postpends.
Table 50 Suggested FIFO Size Encoding
FIFO Size
(blocks)
FIFO Size
(cells)
FIFO Size
(bytes)
Bandwidth
1
2
128
Below STS-1
2
4
256
STS-1 or less
6
12
768
STS-3
24
48
3072
STS-12 or STS-48
96
192
12288
STS-48
FIFO type – this is a single bit which sets the FIFO in either POS mode (1) or ATM mode (0).
This bit must be set to logic 0 for all PHYs in the Input and Output SDQs, and to logic 1 for all
PHYs in the Packet Bypass SDQ. This bit is specified in the FIFO indirect configuration register
(FIFO_TYPE field).