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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
376
12 Test Features Description
Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital output pins and
the data bus to be held in a high-impedance state. This test feature may be used for board testing.
Test mode registers are used to apply test vectors during production testing of the S/UNI-ATLAS-
3200. Test mode registers (as opposed to normal mode registers) are selected when TRS
(UP_ADDR[11]) is high.
Test mode registers may also be used for board testing. When all of the blocks within the S/UNI-
ATLAS-3200 are placed in test mode 0, device inputs may be read and device outputs may be
forced via the microprocessor interface (refer to the section "Test Mode 0" for details).
In addition, the S/UNI-ATLAS-3200 also supports a standard IEEE 1149.1 five-signal JTAG
boundary scan test port for use in board testing. All digital device inputs may be read and all
digital device outputs may be forced with the exception of the POUT[7:0] bus via the JTAG test
port.
Table 44 Test Mode Register Memory Map
Address
Register
0x000-0x7FF
Normal Mode Registers
0x800
Master Test
0x900
CP Test Register 0
0x901
CP Test Register 1
0x902
CP Test Register 2
…
0xA00-0xFFF
Reserved
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software compatibility with
future, feature-enhanced versions of the product, unused register bits must be written with logic zero.
Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits
should be masked off by software when read.
2. Writable test mode register bits are not initialized upon reset unless otherwise noted.