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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
380
Table 47 Instruction Register
Length - 3 bits
Instructions
Selected Register
Instruction Codes, IR[2:0]
EXTEST
Boundary Scan
000
IDCODE
Identification
001
SAMPLE
Boundary Scan
010
BYPASS
Bypass
011
BYPASS
Bypass
100
STCTEST
Boundary Scan
101
BYPASS
Bypass
110
BYPASS
Bypass
111
Table 48 Identification Register
Length
32 bits
Version number
0H
Part Number
7325H
Manufacturer's identification code
0CDH
Device identification
073250CDH
Table 49 Boundary Scan Register
Length - 514 bits
The boundary scan register has an enable register bit for every output and bidirectional register
bit. However, in order to integrate the boundary scan chain with the chip core and pad ring it was
necessary to select a small number of the boundary scan enables to control all the output and
bidirectional pads. For example, the sdat bus is 64 bits wide and therefore has 64 boundary scan
enables associated with it. Of these 64 enables only one enable is used, the boundary scan enable
associated with the 31
st
bit of the bus. Consequently, a good portion of the scan chain register
bits are unused (marked by a - ).
The boundary scan chain numbering begins at 0 with the first bit shifted out on TDO and ends at
513 with the last bit shifted out on TDO.
Pin
Enable
Register
Bit
Cell Type
Pin
Enable
Register
Bit
Cell Type
bi_dat[15]
0
IN_CELL
saddr[11]
oeb_ocif_eop 257
OUT_CELL
bi_dat[14]
1
IN_CELL
-
258
bi_dat[13]
2
IN_CELL
saddr[12]
oeb_ocif_eop 259
OUT_CELL
bi_dat[12]
3
IN_CELL
-
260
bi_dat[11]
4
IN_CELL
saddr[13]
oeb_ocif_eop 261
OUT_CELL
bi_dat[10]
5
IN_CELL
-
262
bi_dat[9]
6
IN_CELL
saddr[14]
oeb_ocif_eop 263
OUT_CELL