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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
352
Register 0x28B: TxL Calendar Indirect Address and Data
Bit
Type
Function
Default
31:16
Unused
X
15
R
BUSY
X
14
R/W
CALENDAR_ADDR[6]
0
13
R/W
CALENDAR_ADDR[5]
0
12
R/W
CALENDAR_ADDR[4]
0
11
R/W
CALENDAR_ADDR[3]
0
10
R/W
CALENDAR_ADDR[2]
0
9
R/W
CALENDAR_ADDR[1]
0
8
R/W
CALENDAR_ADDR[0]
0
7
R/W
CONFIG_RWB
1
6
Unused
X
5
R/W
CALENDAR_DATA[5]
0
4
R/W
CALENDAR_DATA[4]
0
3
R/W
CALENDAR_DATA[3]
0
2
R/W
CALENDAR_DATA[2]
0
1
R/W
CALENDAR_DATA[1]
0
0
R/W
CALENDAR_DATA[0]
0
The TxL Calendar Indirect Address Data register is an indirect address and data register. The
register is used in both POS and UTOPIA mode of operation to control the weighted round-robin
polling and servicing algorithm. . A description of the calendar is provided in Section 10.1.5.
Generally, the calendar should be set up at device initialization and subsequently be left
unchanged. When the calendar length, or a calendar entry is updated during cell or packet flow,
there may be an impact on polling, which may result in an overrun of the PHY device, or a
spurious TCA Error interrupt. The overrun may occur on any PHY that is currently transferring
data. This impact will be avoided if USE_STPA is logic one while the calendar is being updated
CALENDAR_DATA[5:0]
The CALENDAR_DATA register is provided to program the sequence calendar with PHY ids
between 0 and 47. The calendar consists of a maximum of 128 entries where the
CALENDAR_ADDR is used to access one of the 128 entries to either write or read
CALENDAR_DATA. The length of the calendar is set in the TxL Calendar Length register.
CALENDAR_ADDR[6:0]
The CALENDAR_ADDR register is an indirect address register that is used with
CALENDAR_DATA register. The CALENDAR_ADDR field determines the position in the
calendar which is to be written or read.