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參數(shù)資料
| 型號： | PI7C21P100 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-PORT PCI-X BRIDGE |
| 中文描述： | 2端口PCI - X橋接 |
| 文件頁數(shù)： | 59/77頁 |
| 文件大?。?/td> | 603K |
| 代理商： | PI7C21P100 |
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PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 59 of 77
June 10, 2005 Revision 1.06
8.1.53
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
15:8
Next Capability Pointer
RO
DESCRIPTION
Next Capability Pointer
Returns 90h when read to indicate that there are more list items in the
Capabilities List.
8.1.54
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
31:25
RESERVED
RO
24:22
Secondary Clock
Frequency
DESCRIPTION
Reserved.
Returns 0000000 when read.
Secondary Clock Frequency
Enables the configuration software to determine what mode and what
frequency PI7C21P100 set the secondary bus to the last time the
secondary RST# was asserted.
VALUE MAX CLOCK FREQUENCY
000
conventional mode
001
66 MHz
010
100 MHz
011
133 MHz
1xx
Reserved
Split Request Delayed
0:
The bridge has not delayed a split request
1:
The bridge has delayed a split request because the bridge cannot
forward a transaction to the secondary bus because there isn’t enough
room within the limit specified in the split transaction commitment
limit field in the downstream split transaction control register.
Reset to 0
Split Completion Overrun
0:
PI7C21P100 has accepted all split completions.
1:
PI7C21P100 has terminated a split completion on the secondary
bus with retry or disconnect at the next ADB because the bridge
buffers were full.
Reset to 0
Unexpected Split Completion
0:
No unexpected split completion has been received.
1:
An unexpected split completion has been received with the
requested ID equal to the bridge’s secondary bus number, device
number 00h, and function number 0 on the bridge secondary
interface.
Reset to 0
Split Completion Discarded
0:
No split completion has been discarded.
1:
A split completion moving toward the secondary bus has been
discarded by the bridge because the requester would not accept it.
Reset to 0.
133MHz Capable
Returns 1 when read to indicate PI7C21P100 is capable of 133MHz
operation on the secondary interface.
64-bit Device
Returns a 1 when the AD interface is 64-bits wide on the secondary
bus and 64BIT_DEV#=1. Returns a 0 when 64BIT_DEV#=0.
RO
MIN CLK PERIOD
N/A
15ns
10ns
7.5ns
Reserved
21
Split Request Delayed
RW
20
Split Completion
Overrun
RW
19
Unexpected Split
Completion
RW
18
Split Completion
Discarded
RW
17
133MHz Capable
RO
16
64-bit Device
RO
8.1.55
PCI-X BRIDGE PRIMARY STATUS REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
DESCRIPTION
31:22
RESERVED
RO
Reserved.
Returns 00000000 when read.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C21P100NH | 2-PORT PCI-X BRIDGE |
| PI7C7100BNA | PCI Bus Interface/Controller |
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C21P100B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BEVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C21P100BNH | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BNHE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI-X to PCI-XBridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C21P100EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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