參數(shù)資料
型號(hào)： PI7C21P100
廠商： Pericom Semiconductor Corp.
英文描述： 2-PORT PCI-X BRIDGE
中文描述： 2端口PCI - X橋接
文件頁(yè)數(shù)： 10/77頁(yè)
文件大?。?/td> 603K
代理商： PI7C21P100
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 10 of 77
June 10, 2005 Revision 1.06
3
SIGNAL DEFINITIONS
3.1
SIGNAL TYPES
Signal Type
I
O
P
TS
STS
Description
Input Only
Output Only
Power
Tri-State bi-directional
Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when
deasserting.
Open Drain
Internal pull-up on signal
Internal pull-down on signal
OD
IU
ID
3.2
SIGNALS
Signal names that end with “#” are active LOW.
3.2.1
PRIMARY BUS INTERFACE SIGNALS
Name
P_AD[31:0]
Pin #
J23, M21, M22, L21,
L22, G23, K20, E23,
K21, D23, K22, J21,
J22, H21, H22, G21,
B20, G22, F20, F22,
D18, C19, C17, B17,
A20, C16, B16, A19,
C15, B14, C13, B13
A15, D14, B18, A13
Type
TS
Description
Primary Address / Data:
Multiplexed address and data
bus. Address is indicated by P_FRAME# assertion.
Write data is stable and valid when P_IRDY# is asserted
and read data is stable and valid when P_TRDY# is
asserted. Data is transferred on rising clock edges when
both P_IRDY# and P_TRDY# are asserted. During bus
idle, PI7C21P100 drives P_AD[31:0] to a valid logic
level when P_GNT# is asserted.
Primary Command/Byte Enables:
Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. After that, the initiator drives the byte enables
during data phases. During bus idle, PI7C21P100 drives
P_CBE[3:0]# to a valid logic level when P_GNT# is
asserted.
Primary Parity.
P_PAR is even parity of P_AD[31:0]
and P_CBE[3:0] (i.e. an even number of 1’s). P_PAR is
valid and stable one cycle after the address phase
(indicated by assertion of P_FRAME#) for address
parity. For write data phases, P_PAR is valid one clock
after P_IRDY# is asserted. For read data phase, P_PAR
is valid one clock after P_TRDY# is asserted. Signal
P_PAR is tri-stated one cycle after the P_AD lines are
tri-stated. During bus idle, PI7C21P100 drives P_PAR
to a valid logic level when P_GNT# is asserted.
Primary FRAME (Active LOW).
Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of P_FRAME#
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven HIGH for one cycle.
Primary IRDY (Active LOW).
Driven by the initiator
of a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven HIGH for one cycle.
P_CBE[3:0]#
TS
P_PAR
C18
TS
P_FRAME#
A17
STS
P_IRDY#
A16
STS
相關(guān)PDF資料
PDF描述
PI7C21P100NH 2-PORT PCI-X BRIDGE
PI7C7100BNA PCI Bus Interface/Controller
PI7C7100 3-Port PCI Bridge
PI7C7100CNA 3-Port PCI Bridge
PI7C7300 3-PORT PCI-to-PCI BRIDGE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C21P100B 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE
PI7C21P100BEVB 功能描述:界面開(kāi)發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C21P100BNH 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE
PI7C21P100BNHE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI-X to PCI-XBridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C21P100EVB 功能描述:界面開(kāi)發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*