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PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 49 of 77
June 10, 2005 Revision 1.06
8.1.33
BRIDGE CONTROL REGISTER – OFFSET 3Ch
BIT
FUNCTION
31:28
RESERVED
27
Discard Timer
P_SERR# Enable
TYPE
RO
RW
DESCRIPTION
Reserved
. Returns 0h when read.
Discard Timer P_SERR# Enable
0:
Does not assert P_SERR# on the primary interface as a result of
the expiration of either the primary discard timer or secondary
discard timer.
1:
Asserts P_SERR# on the primary interface as a result of the
expiration of either the primary discard timer or secondary discard
timer.
This bit is ignored in PCI-X mode. Reset to 0h.
Master Timeout Status
0:
No discard timer error
1:
Discard timer error (from primary or secondary discard timer)
This bit remains 0 when in PCI-X mode. Reset to 0h.
Secondary Master Timeout Status
0:
The secondary discard timer counts 2
15
PCI clock cycles.
1:
The secondary discard timer counts 2
10
PCI clock cycles.
If the secondary interface is in PCI-X mode, this bit is ignored.
Reset to 0h.
Primary Master Timeout Status
0:
The primary discard timer counts 2
15
PCI clock cycles.
1:
The primary discard timer counts 2
10
PCI clock cycles.
If the primary interface is in PCI-X mode, this bit is ignored. Reset
to 0h.
Fast Back-to-Back Transaction Enable
Designates PI7C21P100 does not generate fast back-to-back
transactions. Returns 0 when read.
Secondary Interface Reset
0:
Does not force the assertion of S_RST# on the secondary interface
1:
Forces the assertion of S_RST# on the secondary interface.
Reset to 0h.
Master Abort Mode
0:
Do not report master aborts. Returns FFFFFFFFh on reads and
discard data on writes.
1:
Report master aborts by signaling target abort if possible or by
asserting SERR# (if enabled).
If in PCI-X mode, PI7C21P100 will return a split completion
message, leaving the host bridge to return FFFFFFFFh on any non-
posted transaction when the non-posted transaction ends in a master
abort.
Reset to 0h.
Reserved.
Returns 0 when read.
VGA Enable
0:
Does not forward VGA compatible memory and I/O addresses
from the primary to secondary interface unless they are enabled for
forwarding by the defined I/O and memory address ranges.
1:
Forwards VGA compatible memory and I/O addresses from the
primary to secondary interface (if the I/O enable and Memory enable
bits are set) independent of the defined I/O and memory address
ranges and independent of the ISA enable bit.
ISA Enable
0:
Forward downstream all I/O addresses in the address defined by
the I/O base and limit registers.
1:
Forward upstream all I/O addresses in the address range defined
by the I/O base and limit registers that are in the first 64KB of PCI
I/O address space
Reset to 0h.
S_SERR# Enable
0:
Disable the forwarding of S_SERR# to P_SERR#
1:
Enable the forwarding of S_SERR# to P_SERR#.
Reset to 0h.
26
Master Timeout Status
RWC
25
Secondary Master
Timeout Status
RW
24
Primary Master Timeout
Status
RW
23
Fast Back-to-Back
RO
22
Secondary Interface
Reset
RW
21
Master Abort Mode
RW
20
19
RESERVED
VGA Enable
RO
RW
18
ISA Enable
RW
17
S_SERR# Enable
RW