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參數(shù)資料
| 型號： | PI7C21P100 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-PORT PCI-X BRIDGE |
| 中文描述： | 2端口PCI - X橋接 |
| 文件頁數(shù)： | 33/77頁 |
| 文件大?。?/td> | 603K |
| 代理商： | PI7C21P100 |
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PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 33 of 77
June 10, 2005 Revision 1.06
5.1
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when those
transactions cross PI7C21P100.
The following general ordering guidelines govern transactions crossing PI7C21P100:
Requests terminated with target retry can be accepted and completed in any order with
respect to other transactions that have been terminated with target retry. If the order of
completion of delayed or split requests is important, the initiator should not start a second
delayed or split transaction until the first one has been completed. If more than one
delayed or split transaction is initiated, the initiator should repeat all retried requests,
using some fairness algorithm. Repeating a delayed or split transaction cannot be
contingent on completion of another delayed transaction. Otherwise, a deadlock can
occur.
Write transactions flowing in one direction have no ordering requirements with respect to
write transactions flowing in the other direction. PI7C21P100 can accept posted write
transactions on both interfaces at the same time, as well as initiate posted write
transactions on both interfaces at the same time.
The acceptance of a posted memory or memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master. This is
true for PI7C21P100 and must also be true for other bus agents. Otherwise, a deadlock
can occur.
PI7C21P100 accepts posted write transactions, regardless of the state of completion of
any delayed transactions being forwarded across PI7C21P100.
5.2
ORDERING RULES
Table 5-1
SUMMARY OF TRANSACTION ORDERING IN PCI MODE
and
Table 5-2 show the ordering relationships of all the transactions and refers by number to the
ordering rules that follow.
Table 5-1 SUMMARY OF TRANSACTION ORDERING IN PCI MODE
Pass
Posted Write
Delayed
Read
Request
Yes
Yes
Yes
Yes
Yes
Delayed
Write
Request
Yes
Yes
No
Yes
Yes
Delayed
Read
Completion
Yes
Yes
Yes
Yes
Yes
Delayed
Write
Completion
Yes
Yes
Yes
Yes
No
Posted Write
Delayed Read Request
Delayed Write Request
Delayed Read Completion
Delayed Write Completion
1. If the relaxed ordering bit is set in PCI to PCI mode, or the enable relaxed ordering bit in the primary and/or
secondary data buffering control registers is set in any other mode, read completions can pass memory writes.
No
No
No
No
1
No
Table 5-2 SUMMARY OF TRANSACTION ORDERING IN PCI-X MODE
Pass
Memory
Write
No
No
No
Split Read
Request
Yes
Yes
Yes
Split Write
Request
Yes
Yes
No
Split Read
Completion
Yes
Yes
Yes
Split Write
Completion
Yes
Yes
Yes
Posted Write
Delayed Read Request
Delayed Write Request
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C21P100NH | 2-PORT PCI-X BRIDGE |
| PI7C7100BNA | PCI Bus Interface/Controller |
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C21P100B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BEVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C21P100BNH | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BNHE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI-X to PCI-XBridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C21P100EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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