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參數(shù)資料
| 型號(hào)： | P62000NLG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC64 |
| 封裝： | ROHS COMPLIANT, QFN-64 |
| 文件頁數(shù)： | 61/62頁 |
| 文件大?。?/td> | 1221K |
| 代理商： | P62000NLG |
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IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
8
IDTP62000
REV E 050510
CONFIDENTIAL
45
CSN2
A-I
Phase 2 current sense - negative input.
46
CSP2
A-I
Phase 2 current sense - positive input.
47
CSN3
A-I
Phase 3 current sense - negative input.
48
CSP3
A-I
Phase 3 current sense - positive input.
49
CSN4
A-I
Phase 4 current sense - negative input.
50
CSP4
A-I
Phase 4 current sense - positive input.
51
IMON
A-O
Total load current monitoring output pin. It is used with the PSI# to properly handle the
dynamic phase switching for higher efficiency. IMON is limited to a max voltage of 1.1 V so
as not to damage the CPU input.
52
VID7
D-I/O
The voltage identification pin VID7, connects to CPU. (See Note 1)
53
VID6
D-I/O
The voltage identification pin VID6, connects to CPU. (See Note 1)
54
VID5
D-I/O
The voltage identification pin VID5, connects to CPU. (See Note 1)
55
VID4
D-I/O
The voltage identification pin VID4, connects to CPU. (See Note 1)
56
VID3/SVC
D-I/O
The voltage identification pin VID3, connects to CPU. (See Note 1)
57
VDD
P-I
+5V (nominal) supply pin for “l(fā)ower” voltage circuits.
58
VID2/SVD
D-I/O
The voltage identification pin VID2, connects to CPU. (See Note 1)
59
VID1/PVI_SVI#
D-I/O
The voltage identification pin VID1, connects to CPU. (See Note 1)
60
VID0
D-I/O
The voltage identification pin VID0, connects to CPU. (See Note 1)
61
SIFDAT/DVC[1]
I2C-O
GP-OUT
Serial data output pin for the SIF bus.
When in GPO mode, this pin serves as the DVC[1] logical output and requires a 4 k
Ω
pull-down resistor.
62
SIFCLK/DVC[0]
I2C-O
GP-OUT
Serial clock output pin for the SIF bus.
When in GPO mode, this pin serves as the DVC[0] logical output and requires a 4 k
Ω
pull-down resistor.
63
SMBCLK
A-I/O
Clock input pin for the system management bus and is compliant with the SMBus
specification.
64
SMBDAT
A-I/O
Data input pin for the system management bus and is compliant with the SMBus
specification.
Pin #
Pin Name
Pin Type
Pin Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P62000NLG8 | 制造商:Integrated Device Technology Inc 功能描述:PWM Controller 64-Pin QFN EP T/R 制造商:Integrated Device Technology Inc 功能描述:64 NLG (GREEN) - Tape and Reel |
| P6-20024 | 制造商:OTTO Engineering Inc 功能描述:S/A P6-20017 EX W/ |
| P6-20029 | 制造商:OTTO Engineering Inc 功能描述:S/A P6-20021 EX 2PDT |
| P6-20030 | 制造商:OTTO Engineering Inc 功能描述:S/A P6-20029 EX SPDT |
| P6-20050 | 制造商:OTTO Engineering Inc 功能描述:S/A P6-20018 EX |
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