參數(shù)資料
型號(hào)： P62000NLG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 穩(wěn)壓器
英文描述： DUAL SWITCHING CONTROLLER, QCC64
封裝： ROHS COMPLIANT, QFN-64
文件頁(yè)數(shù)： 37/62頁(yè)
文件大小： 1221K
代理商： P62000NLG
IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
42
IDTP62000
REV E 050510
CONFIDENTIAL
Load Line and RFB Selection
The ISENSE currents from the configured phases are processed and the average value is outputed at the DROOP pin. The
droop current is derived from all the configured phases regardless of whether any are disabled due to operation in a power
savings mode.Connecting the DROOP and FB pins together enables the current sourced in the DROOP pin to develop a
voltage across the FB resistor and implement a load line. Use Equation 5 to select the FB resistor value.
RFB = RDROOP x RSENSE x # of configured phases / DCR (equation 5)
For a four phase converter with DCR = 0.8 mohm, RISENSE = 619 ohms, and load line impedance of 1.4 mohms;
RFB = 1.4 mohm x 619 ohm x 4 / 0.8 mohm = 4.33 kohm
IMON Load Current Signal
The ISENSE currents from the configured phases are summed, processed, and sent out to the IMON pin. Use equation 6 to
select the RIMON resistor value to program the IMON gain for a particular ICCMAX. Refer to the appropriate Intel VR11.1
specification for information on ICCMAX. An appropriate CIMON capacitor should be placed in parallel with the RIMON
resistor to ensure the RC time constant exceeds 300S.
RIMON = VIMONMAX x RISENSE x # of configured phases / (ICCMAX x DCR) (equation 6)
For a four phase converter with DCR = 0.8 mohm, ICCMAX of 120A, RISENSE = 619 ohms, and VIMONMAX = 0.95V;
RIMON = 0.95V * 619 ohms * 4 / (120A x 0.8mohm) = 24.5kohm
VID Programming
The IDTP62000 supports the four VID (voltage identification) tables; Intel VR10.x, Intel VR11.x, AMD 6 bit parallel VID
(PVID), and AMD 7 bit serial VID (SVID). The VID_SEL pin must be configured to select the appropriate VID table.
Connect the VID_SEL pin to ground (GND) to select VR10.x 7 bit VID
Float the VID_SEL pin or bias it to a voltage between 0.8V and 1.8V to select VR11.x 8 bit VID
Connect the VID_SEL pin to 5V (VDD) to select an AMD VID
– If VID1 is low when the IDTP62000 is enabled 7 bit SVID mode is activated
– If VID1 is high when the IDTP62000 is enabled 6 bit PVID mode is activated
For Intel modes the VID pins are internally biased high to 1.2V logic levels. For AMD modes the pins are internally biased
low. In AMD SVI mode VID2 is the SVD input, VID3 is the SVC input, and VID [7:4] and VID [1:0] are biased low internally.
In AMD SVI mode the boot voltage is determined by the SVC (VID3) and SVD (VID2) bias upon enable as follows:
The VID inputs are monitored and, if stable for 200ns, the IDTP62000 recognizes the new code and changes the internal
DAC reference to the new level. In Intel modes the internal reference voltage transitions up at a fixed rate of 12.5mV per
microsecond and down at 6.25mV per microsecond. In AMD mode the reference voltage transitions at a fixed rate of
3.125mV per microsecond.
SVC
SVD
Output Voltage (V)
00
1.1
01
1.0
10
0.9
11
0.8
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