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參數(shù)資料
| 型號： | P62000NLG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC64 |
| 封裝： | ROHS COMPLIANT, QFN-64 |
| 文件頁數(shù)： | 33/62頁 |
| 文件大?。?/td> | 1221K |
| 代理商： | P62000NLG |
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IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
39
IDTP62000
REV E 050510
CONFIDENTIAL
VR_HOT Alert – Command Code: 08h, Data: 00h, 01h
The IDTP62000 sends this command every time the VR_HOT status changes. The command can be disabled by IDTP62000
register setting (SIF_CMD_EN[1]). When not in DVC mode, this command is sent upon each change in VR_HOT status. The
sending of these SIF commands will be entirely independent of the setting and resetting of the CSR bit VRHOT_ALERT.
VR_FAN Alert – Command Code: 09h, Data: 00h, 01h
The IDTP62000 sends this command every time the VR_FAN status changes. The command can be disabled by the
SIF_CMD_EN[0] register setting. When not in DVC mode, this command is sent upon each change in VR_FAN status. The
sending of these SIF commands will be entirely independent of the setting and resetting of the CSR bit VRFAN_ALERT.
Interaction of SIF commands with DVC mode
When DVC is enabled, the following table describes the impact on DVC status for each of these SIF commands:
Table 12: DVC Action in Conjunction with SIF Commands
DVC GPO Interface
If the DEV_CTRL1 fields are programmed such that GPO_EN = 1b and SIF_EN = 0b, then the SIF interface is disabled and
the DVC GPO bus is enabled. The SIF_EN bit always takes priority if enabled.
The purpose of the DVC GPO bus is to provide backward compatibility for legacy ICS clock generator chips. This data bus
only delivers the DVC[1:0] information to the clock generator chip via the SIFDAT and SIFCLK pins. When operating in GPO
mode, these pins must never drive their output above 3.765V. One means of accomplishing this is to limit the drive for logical
high outputs so that an external resistor can be used to pull the voltage on each of these pins down.
SMBus Interface
The IDTP62000 has an SMBus programming interface that is compatible with the System Management Bus (SMBus)
Specification Version 2.0, dated August 3, 2000. This interface is used to program the Command and Status registers (CSR).
The designated pins are SMBDAT for data and SMBCLK for the clock. The SMBus interface in the IDTP62000 provides for
slave mode operation only. The address of the 7 bit interface is either 0x78 or 0x79 where the LSB of the address is
determined by detecting whether the SS/SMBA0 pin is high or low at powerup. The pin value is latched when the internal
POR de-asserts so that subsequent changes to the SS/SMBA0 pin do not affect the LSB bit.
Table 13: SMBus Address Determination
Comm and
Summ ary of DVC consequence
PSI S tatus
DVID_ EN = 1: disable DVC until PSI status changes to de asserted
DVID_ EN = 0: contin ue in DVC mode
OCP alert
Shut down, DVC resumes after reset
OV P alert
Shut down, DVC resumes after reset
VR_HOT alert
Force to DVC00 until VR_NOT is deasserted
VR_FAN alert
Force to DVC00 until VR_FAN is deasserted
SS/SMBA0 at Power On
SMBus Address
L
0x78
H
0x79
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