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參數(shù)資料
| 型號： | P62000NLG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC64 |
| 封裝： | ROHS COMPLIANT, QFN-64 |
| 文件頁數(shù)： | 18/62頁 |
| 文件大?。?/td> | 1221K |
| 代理商： | P62000NLG |
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IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
25
IDTP62000
REV E 050510
CONFIDENTIAL
AMD PVI/SVI Dynamic VID Transitions
In AMD mode, D-VID can “jump” or change by more than one bit step at a time. If the new VID code is stable for 200 ns, the
controller will recognize the change and begin to adjust the DAC at a rate of 3.125 mV per 1 s until the VID and DAC are
equal. This means that the total time for a change is dependant on the size of the D-VID change.
Chip Enable and Disable
Proper function of both the controller and the driver requires that the bias voltage applied at VDD, UVLO_PVCC and
UVLO_VTT must reach the appropriate threshold voltages as defined in Table 1 and Table 2. The hysteresis between the
rising and falling thresholds assures that once enabled, the product will not turn off unless there is a substantial drop in
supply voltage bias. A recommended connection for the UVLO_PVCC pin is a voltage divider on the 12 volt supply such that
when UVLO_PVCC goes above 0.8 V, the driver will already have been powered up. A fixed hysteresis of 65 mV is internally
added such that UVLO_PVCC will not be deactivated until the level drops to 0.735 V.
Similarly, UVLO_VTT uses a voltage divider on the motherboard's VTT supply such that when UVLO_VTT goes above 0.8
V, the driver will already have been powered up. Hysteresis of 65 mV (typical) is again added such that UVLO_VTT will not
be deactivated until the level drops to 0.735 V.
There are two means by which the controller can be reset: the internal power-on (POR) reset and the external reset pins,
UVLO_PVCC and UVLO_VTT. The internal power-on reset is asserted when the device determines that VDD has reached
the voltage defined in Table 2. The external UVLO_PVCC and UVLO_VTT are asserted when each pin has reached the
voltage defined in Table 2. POR and both reset pins must be asserted to allow normal operation. Deasserting and then
reasserting either one will cause the IDTP62000 to immediately reset and perform a soft start. For a POR reset, all CSR
registers are returned to their initial, power-on condition (including fuse and OTP values). For a reset cycle caused by either
UVLO_PVCC or UVLO_VTT (called a soft reset) the only registers that will be reset are the status registers in DEV_STAT1
and DEV_STAT2. A soft reset can also be induced by writing a 1 to the SOFT_RESET CSR bit.
Initialization
During power up, the device is tolerant of any permutation of power ramping of the 5 V and 12 V supplies.
It is important to properly determine the number of phases and the appropriate VID table selection before the system starts
up. This is done by appropriately connecting VID_SEL and PWM4 pins.
During internal power-on reset, the VID_SEL pin state shall determine which VID table is used. Its value is set by an external
pull-up or pull-down resistor where pull-up selects the VRD11 8-bit VID table; pull-down selects the VRD10 6-bit VID table;
and floating selects AMD PVI or SVI VID table.
Selection of Phase Number
The IDTP62000 determines the number of phases to be enabled by evaluating the state of the PWM4 pin at power-up. If
PWM4 is pulled high, 3 phase mode is selected. If PWM4 is pulled low, 2-phase mode is selected. When used in a 4 phase
configuration, an external single phase driver must be used and connected to PWM4. Leakage resistors on this driver's input
must cause the PWM4 signal to float to midrail during power up. When this midrail condition is detected, 4 phase mode is
selected. The external single phase driver must be powered with the same VDD that is used to power the IDTP62000. The
number of phases can be changed using the PhaseN fields in DEV_CTRL1[3:0] register.
The selection table is shown below:
Table 4: PWM4 Level vs. Number of Phases
PWM4 Level
High
MID Voltage
Low
Number of Phases
3-phase
4-phase
2-phase
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| P62000NLG8 | 制造商:Integrated Device Technology Inc 功能描述:PWM Controller 64-Pin QFN EP T/R 制造商:Integrated Device Technology Inc 功能描述:64 NLG (GREEN) - Tape and Reel |
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| P6-20029 | 制造商:OTTO Engineering Inc 功能描述:S/A P6-20021 EX 2PDT |
| P6-20030 | 制造商:OTTO Engineering Inc 功能描述:S/A P6-20029 EX SPDT |
| P6-20050 | 制造商:OTTO Engineering Inc 功能描述:S/A P6-20018 EX |
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