參數(shù)資料
型號(hào): P62000NLG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 穩(wěn)壓器
英文描述: DUAL SWITCHING CONTROLLER, QCC64
封裝: ROHS COMPLIANT, QFN-64
文件頁(yè)數(shù): 38/62頁(yè)
文件大?。?/td> 1221K
代理商: P62000NLG
IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
43
IDTP62000
REV E 050510
CONFIDENTIAL
Registers
Memory Map
Register Bit-Type Descriptions
The following codes are used to describe register bit types:
Command and Status Registers
Offset
Register Name
Description
0x00
DEV_CTRL1
Device control register
0x01
DEV_CTRL2
Device control register
0x02
DEV_STAT1
Device status register
0x03
DEV_STAT2
Device status register
0x04
VID_CTRL
VID control register
0x05
VID_DAC_STAT
VID code at input of DAC status register
0x06
VID_INPUT_STAT
Loaded VID from pins status and control register
0x07
OVP_UVP_ADJUST
Over-voltage offset level register
0x08
PSI_CTRL
PSI control register
0x09
TM_STAT
TM value + TC_OFFSET status register
0x0A
TEMP_OFFSET
TM_OFFSET and TC_OFFSET register
Dynamic Efficiency Control Registers
Offset
Register Name
Description
0x20
DEC_CTRL
DEC control register
0x21
DEC_SS_DELAY
Soft start to DEC delay register
0x22
DEC_WIN
DEC window filter register
0x23
DEC_LEVEL1_H
DEC one phase load level upper threshold register
0x24
DEC_LEVEL1_L
DEC one phase load level lower threshold register
0x25
DEC_LEVEL2_H
DEC two phase load level upper threshold register
0x26
DEC_LEVEL2_L
DEC two phase load level lower threshold register
0x27
DEC_LEVEL3_H
DEC three phase load level upper threshold register
0x28
DEC_LEVEL3_L
DEC three phase load level lower threshold register
Dynamic Voltage Change Registers
Offset
Register Name
Description
0x30
DVC_CTRL
DVC control register
0x31
DVC_WIN
DVC window filter register
0x32
DVC_DFC_DELAY
DVC Vcore delay register
0x33
DVC_SS_DELAY
Soft start to DVC delay register
0x34
DVC00_VID_OFFSET
DVC00 mode DVID is offset register
0x35
DVC01_VID_OFFSET
DVC01 mode DVID is offset register
0x36
DVC10_VID_OFFSET
DVC10 mode DVID is offset register
0x37
DVC11_VID_OFFSET
DVC11 mode DVID is offset register
0x38
DVC_LEVEL1_H
DVC load level1 upper threshold register
0x39
DVC_LEVEL1_L
DVC load level1 lower threshold register
0x3A
DVC_LEVEL2_H
DVC load level2 upper threshold register
0x3B
DVC_LEVEL2_L
DVC load level2 lower threshold register
0x3C
DVC_LEVEL3_H
DVC load level3 upper threshold register
0x3D
DVC_LEVEL3_L
DVC load level3 lower threshold register
Type
Description
R/W
Read/Write: Register bit may be written and read by the user
RC
Read Clear: Register bit may not be written by user (writes are ignored), but is set by the IDTP62000 device
when appropriate. When read by the user, the bit will be cleared.
RO
Read Only: Register bit may not be written by user (writes are ignored), but is set by the IDTP62000 device.
When read by the user, the bit retains its value.
WO
Write Only: Writing the register initiates some sort of one-time action. Reading the register always returns 0, as
though the address was undefined. In fact, there may be no physical register present.
R/W or
RO
Read/Write or Read Only: Depending on the value of a controlling CSR bit, this register may or may not be
written. It may always be read.
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