參數(shù)資料
型號(hào): P62000NLG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 穩(wěn)壓器
英文描述: DUAL SWITCHING CONTROLLER, QCC64
封裝: ROHS COMPLIANT, QFN-64
文件頁數(shù): 35/62頁
文件大小: 1221K
代理商: P62000NLG
IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
40
IDTP62000
REV E 050510
CONFIDENTIAL
Applications Information
PWM Modulation and Regulation
The IDTP62000 implements voltage mode control with trailing edge modulation. Per phase switching frequency is
programmed by an external resistor connected from the ROSC pin to GND according to equations (1) and (2).
ROSC = 1 / FSW x 40pF (equation 1)
FSW = 1 / ROSC x 40pF (equation 2)
The voltage mode ramp amplitude is typically 2.4V over the full switching period with duty cycle limited to 93% to ensure
proper driver bootstrap operation. The error amp provides high gain, bandwidth, and slew rate using type 3 compensation.
A DAC (Digital to Analog Converter) sets the error amp reference voltage and is biased to the converter remote sense ground
to eliminate the need for a differential remote sense amplifier and errors factors associated with it. Converter output voltage
offset and load line are implemented through bias currents flowing into the feeback resistor. Figure 32 depicts the error
amplifier configuration.
Current sharing among active phases is achieved by controlling the duty cycle of each phase through a current mode
feedback loop.
Figure 32: Error Amplifier Configuration
Reference Current (IREF) and Load Line Temperature Compensation Enable
To enable the IDTP62000 to accurately process current information an accurate reference current is created by placing an
external 40.2kohm ±1% accurate resistor between IREF and either GND or VDD. Connecting the resistor to GND enables
load line temperature compensation while connecting it to VDD disables it. The voltage across the IREF resistor is regulated
to 0.8V creating a nominal 19.9A reference current. Load line temperature compensation is useful for typical inductor
current sense applications but should be disabled if a zero TC inductor DCR or precision current sense resistors are used.
+
-
EA
RFB
IDROOP
DAC
VID_SEL
VID[7:0]
VREF
Bandgap
Reference
IOFS_L
IOFS_H
FB
DROOP
R3
C3
C1
R1
C2
VCORE
COMP
EA_OUT
RGND
EXTERNAL
INTERNAL
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