參數(shù)資料
型號(hào)： P62000NLG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 穩(wěn)壓器
英文描述： DUAL SWITCHING CONTROLLER, QCC64
封裝： ROHS COMPLIANT, QFN-64
文件頁(yè)數(shù)： 28/62頁(yè)
文件大?。?/td> 1221K
代理商： P62000NLG
IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
34
IDTP62000
REV E 050510
CONFIDENTIAL
Table 9: Address and Data Byte Formats
Subsequent data bytes, if any are ignored. The VID[6:0] codes will be interpreted as follows:
Table 10: VID Codes for AMD PVI/SVI SVI Mode
If a valid VID code has not been received by the end of the soft start period, the device will regulate VCORE to a
predetermined voltage based on the connections of the SVC and SVD pins (VID[3:2]) during power-up per the AMD PVI/SVI
specification as follows:
If an “OFF” code is received, then LGATE, UGATE, and PGOOD will be immediately brought low until the next valid VID code
is received. At that time, the soft start sequence will begin to bring VCORE to the voltage indicated by the new VID code.
Serial Interface (SIF)
The Serial Interface (SIF) is similar to an IC communication architecture but operates at 666.7 kHz. The SIF provides the
ability for the IDTP62000 to communicate information to the PC clock generator. The IDTP62000 is the master and the
9CPS4592 is the slave. The SIF is a two wire interface, serial data (SIFDAT) and serial clock (SIFCLK). The IDTP62000
master will never read from the 9CPS4592, so the SIFDAT traffic is unidirectional. To avoid contention issues between
SMBus write operations and SIF read operations on a Command and Status Register (CSR) the SIF interface does not read
CSRs during any SMBus is write operations. The typical system block diagram using the SIF is shown in figure 26. Figure
28 and Figure 29 are reference examples showing the relationship and interaction between the IDTP62000 and the
9CPS4592.
Address Byte Format
Data Byte Format
[6:4]
Always 110b
7
Ignored
3
Reserved
2
Ignored
1
If set then the following data byte
contains the VID
0
Ignored
[6:0]
VID[6:0]
VID[6:0]
Output Voltage
0x7F to 0x7C
OFF
0x7B to 0x5F
0.375 V
0x5E to 0x00
1.55 - 0.0125 * VID[6:0] V
(1.55 V to 0.375 V)
Vid[3:2]
Voltage
00b
1.1 V
01b
1.0 V
10b
0.9 V
11b
0.8 V
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