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參數(shù)資料
| 型號： | ORT82G5-2FN680I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 69/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
53
Parallel loopback at MUX/DEMUX boundary excluding SERDES (near end)
The three loopback modes are described in more detail in the following sections. As noted earlier, other specialized
loopback modes can be obtained by conguration of the FPGA logic or by connections external to the FPSC.
High-Speed Serial Loopback at the CML Buffer Interface
The high-speed serial loopback mode has the serial transmit signals looped back internally to the serial receive cir-
cuitry. The internal loopback path is from the input connection to the transmit CML buffer to the output connection
from the receive CML buffer. The data are sourced on the TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal
lines and received on the MRWDxx[39:0] signal lines. The serial loopback path does not include the high-speed
input and output buffers. If TESTEN_xx is set, the HDOUTP_xx and HDOUTN_xx outputs are active in this mode
while the CML input buffers are powered down. The device is otherwise in its normal mode of operation. This mode
is normally used for tests where the data source and destination are on the same card and is the basic loopback
path shown earlier in Figure 32(a).
The data rate selection bits, TXHR and RXHR, in the channel conguration registers must be congured to carry
the same value. Table 19 and Table 20 summarize the settings of the control interface register conguration bits for
high-speed serial loopback.
Table 19. High-Speed Serial Loopback Conguration Bit Denitions for the ORT42G5
Table 20. High-Speed Serial Loopback Conguration Bit Denitions for the ORT82G5
Register
Address
Bit Value
Bit Name
Comments
30022, 30032, 30122,
30132
Bit 0 = 0 or 1
TXHR
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
Bit 7 = 0 or 1
8B10BT
Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
30023, 30033, 30123,
30133
Bit 0 = 0 or 1
RXHR
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
Bit 3 = 0 or 1
8B10BR
Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
30801, 30901
Bit 2 = 1 (Channel C)
Bit 3 = 1 (Channel D)
LOOPENB_xx Set any of the bits 0-3 to 1 to do serial loopback on the corre-
sponding channel.* The high speed serial outputs will not be
active.
*This test mode can also be set using TESTEN_xx in place of LOOPENB_xx. In that case, Test Mode must be set to 00000.
Register
Address
Bit Value
Bit Name
Comments
30002, 30012, 30022,
30032, 30102, 30112,
30122, 30132
Bit 0 = 0 or 1
TXHR
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
Bit 7 = 0 or 1
8B10BT
Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
30003, 30013, 30023,
30033, 30103, 30113,
30123, 30133
Bit 0 = 0 or 1
RXHR
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
Bit 3 = 0 or 1
8B10BR
Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-2FN680I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C2 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs |
| ORT82G5-3F680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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