參數(shù)資料
型號： ORT82G5-2FN680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 58/119頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
43
Internal Clock Signals at the FPGA/Core Interface for the ORT82G5
There are several clock signals dened at the FPGA/Embedded Core interface in addition to the external reference
clock for each SERDES quad. All of the ORT82G5 clock signals are shown in Figure 24 and are described follow-
ing the gure.
Figure 24. ORT82G5 Clock Signals (High Speed Serial I/O Also Shown)
REFCLKP_[A:B], REFCLKN_[A:B]:
These are the differential reference clocks provided to the ORT82G5 device as described earlier. They are used as
the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbps, the reference clocks
will be at a frequency of 156.25 MHz.
RWCK[AA:BD]:
These are the low-speed receive clocks from the embedded core to the FPGA across the core-FPGA interface.
These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCK_AA
belongs to Channel AA, RWCK_AB belongs to channel AB and so on. With a reference clock input of 156.25 MHz,
these clocks operate at 78.125 MHz.
RCK78[A:B]:
These are muxed outputs of RWCKA[A:D] and RWCKB[B:D] respectively. With a reference clock input of 156.25
MHz, these clocks operate at 78.125 MHz.
FPGA
Logic
Common Logic, Quad A
Channel AA
Channel AB
Channel AD
Channel AC
Common Logic, Quad B
Channel BA
Channel BB
Channel BD
Channel BC
RCK78A
TCK78A
RSYS_CLK_A1
TSYS_CLK_AA
RWCKAA
RWCKAB
TSYS_CLK_AB
RWCKAC
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_AD
RWCKAD
RCK78B
TCK78B
RSYS_CLK_B1
TSYS_CLK_BA
RWCKBA
RWCKBB
TSYS_CLK_BB
RSYS_CLK_B2
RWCKBD
RWCKBC
TSYS_CLK_BC
TSYS_CLK_BD
REFCLK[P:N]_A
2
HDIN[P:N]_AC
2
HDOUT[P:N]_AD
HDIN[P:N]_AD
2
HDOUT[P:N]_AC
HDOUT[P:N]_AB
2
HDIN[P:N]_AB
2
HDOUT[P:N]_AA
2
HDIN[P:N]_AA
2
REFCLK[P:N]_B
HDIN[P:N]_BC
2
HDIN[P:N]_BD
2
HDIN[P:N]_BB
2
HDIN[P:N]_BA
2
HDOUT[P:N]_BA
HDOUT[P:N]_BB
HDOUT[P:N]_BC
HDOUT[P:N]_BD
2
TCK78A
Backplane
Serial
Link
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參數(shù)描述
ORT82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3BM680C2 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs
ORT82G5-3F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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