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參數(shù)資料
| 型號(hào)： | ORT82G5-2FN680I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 31/119頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
19
Since this effect is predictable for a given type of PCB material, it is possible to compensate for this effect in two
ways - transmitter preemphasis and receiver equalization. Each of these techniques boosts the high frequency
components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better
power utilization. It also gives a better signal-to-noise ratio because receiver equalization amplies both the signal
and the noise at the receiver
Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also
degrade the data eye opening at the receiver. In the ORT42G5 and ORT82G5 the degree of transmit preemphasis
can be programmed with a two-bit control from the microprocessor interface as shown in Table 3. The high-pass
transfer function of the preemphasis circuit is given by the following equation, where the value of a is shown in
H(z) = (1 – az
–1)
(1)
Table 3. Preemphasis Settings
Receive Path (Backplane to FPGA) Logic
The receiver section receives high-speed serial data at the external differential CML input pins. These data are fed
to the clock recovery section which generates a recovered clock and retimes the data. Therefore the receive clocks
are asynchronous between channels. The retimed data are deserialized and presented as an 8-bit decoded or a
10-bit unencoded parallel data on the output port. The receiver also optionally recognizes comma characters,
detects code violations and aligns the bit stream to the proper word boundary.
As shown in Figure 6, the basic blocks in the receive path include:
Receive SERDES Block
CML input buffer
Receive PLL
1:10 demultiplexer (DEMUX)
Clock and Data Recovery (CDR) section
10b/8b decoder
1:4 demultiplexer and Embedded Core/FPGA interface
1:4 DEMUX
Low speed parallel Embedded Core/FPGA logic interface
Multi-channel alignment logic
PE1
PE0
Amount of Preemphasis (a)
0
0% (No Preemphasis)
0
1
12.5%
1
0
12.5%
1
25%
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-2FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C2 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs |
| ORT82G5-3F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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