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| 型號(hào)： | ORT82G5-2FN680I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 100/119頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
81
TDI, TCK, TMS
I
If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If
boundary-scan is not selected, all boundary-scan functions are inhibited once conguration is
complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during
conguration. Each pin has a pull-up enabled during conguration.
I/O After conguration, these pins are user-programmable I/O if boundary scan is not used.
1
RDY/BUSY/RCLK
O
During conguration in asynchronous peripheral mode, RDY/RCLK indicates another byte can
be written to the FPGA. If a read operation is done when the device is selected, the same sta-
tus is also available on D7 in asynchronous peripheral mode.
During the master parallel conguration mode, RCLK is a read output signal to an external
memory. This output is not normally used.
I/O After conguration this pin is a user-programmable I/O pin.
1
HDC
O
High During Conguration is output high until conguration is complete. It is used as a control
output, indicating that conguration is not complete.
I/O After conguration, this pin is a user-programmable I/O pin.
1
LDC
O
Low During Conguration
is output low until conguration is complete. It is used as a control out-
put, indicating that conguration is not complete.
I/O After conguration, this pin is a user-programmable I/O pin.
1
INIT
I/O INIT is a bidirectional signal before and during conguration. During conguration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain output,
INIT
is held low during power stabilization and internal clearing of memory. As an active-low
input, INIT holds the FPGA in the wait-state before the start of conguration.
After conguration, this pin is a user-programmable I/O pin.
1
CS0, CS1
I
CS0
and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor con-
guration modes. The FPGA is selected when CS0 is low and CS1 is high. During congura-
tion, a pull-up is enabled.
I/O After conguration, if MPI is not used, these pins are user-programmable I/O pins.
1
RD/MPI_STRB
I
RD
is used in the asynchronous peripheral conguration mode. A low on RD changes D[7:3]
into a status output. WR and RD should not be used simultaneously. If they are, the write strobe
overrides.
This pin is also used as the
MPI data transfer strobe. As a status indication, a high indicates
ready, and a low indicates busy.
WR/MPI_RW
I
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the
FPGA.
In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write
transfer to the FPGA.
I/O After conguration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.
1
PPC_A[14:31]
I
During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus
master utilizing the least-signicant bits of the PowerPC 32-bit address.
MPI_BURST
I
MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high
indicates that the current transfer is not a burst.
MPI_BDIP
I
MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that
the second beat in front of the current one is requested by the master. Negated before the burst
transfer ends to abort the burst data phase.
MPI_TSZ[0:1]
I
MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer
size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
A[21:0]
O
During master parallel mode A[21:0] address the conguration EPROMs up to 4M bytes.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.
1
MPI_ACK
O
In
MPI mode this is driven low indicating the MPI received the data on the write cycle or
returned data on a read cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.
1
Table 40. Pin Descriptions (Continued)
Symbol
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680C | IC TRANCEIVERS FPSC 680FPBGA |
| MSP430F4793IPZ | IC MCU 16BIT 60KB FLASH 100LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-2FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C2 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs |
| ORT82G5-3F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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