參數(shù)資料
型號: OMAP5910(DSP)
英文描述: Dual-Core Processor
中文描述: 雙核處理器
文件頁數(shù): 57/160頁
文件大?。?/td> 1997K
代理商: OMAP5910(DSP)
Functional Overview
45
August 2002 Revised August 2003
SPRS197B
3.6.2 USB Function Peripheral
The USB Function peripheral provides a full-speed Function interface between the MPU and the USB wire.
The module handles USB transactions with minimal MPU intervention and is fully compliant to USB standard.
The USB Function module supports one control endpoint (EP0), up to 15 IN endpoints, and up to 15 OUT
endpoints. The exact endpoint configuration is software-programmable. The specific items of a configuration
for each endpoint are: the size in bytes, the direction (IN, OUT), the type (bulk/interrupt or isochronous), and
the associated endpoint number. The USB Function module also supports the use of three System DMA
channels for IN endpoints and three System DMA channels for OUT endpoints for either bulk/interrupt or
isochronous transactions.
The OMAP5910 device implements a variety of signal-multiplexing options that allow use of the USB Function
peripheral with any one of the three available USB interfaces on the device. One of these interfaces utilizes
an integrated USB transceiver, while the other two require external transceivers. The USB Function can only
utilize one of these ports at a time. The other ports may be used simultaneously by the USB Host controller
peripheral.
3.6.3 Multichannel Buffered Serial Port (McBSP)
The Multichannel Buffered Serial Port (McBSP) provides a high-speed, full-duplex serial port that allow direct
interface to audio codecs, and various other system devices. The MPU public peripheral bus has access to
one McBSP, which is McBSP2.
The McBSP provides:
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
Direct interface to:
T1/E1 framers
MVIP switching-compatible and ST-BUS compliant devices
IOM-2 compliant device
AC97-compliant device
I2S-compliant device
Serial peripheral interface (SPI)
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits
μ
-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
NOTE:
All of the standard McBSP pins are not necessarily available on every McBSP on the
OMAP5910 device.
In the case of the MPU’s McBSP2, the following pins are available:
CLKX and CLKR (transmit and receive clocks)
FSX and FSR (transmit and receive frame syncs)
DX and RX (transmit and receive data)
The functional clock to the McBSP2 peripheral is configurable to the DPLL clock rate with a divider of 1, 2,
4, or 8.
McBSP2 does not have a CLKS external clock reference pin. Therefore, if the McBSP2 Sample Rate
Generator (SRG) is used, the only reference clock available to the Sample Rate Generator is a programmable
clock from the MPU domain.
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