參數(shù)資料
型號(hào)： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 23/160頁
文件大小： 1997K
代理商： OMAP5910(DSP)
Introduction
11
August 2002 Revised August 2003
SPRS197B
RESET STATE:
The state of the terminal at reset.
SUPPLY:
The voltage supply which powers the terminal’s I/O buffers.
NOTE:
Due to the extensive pin multiplexing options which are available on the OMAP5910
device, a software utility is available to ease the process of configuring the pins based on the
peripheral set required by a specific application. The 5910 OMAP Pin Configuration Utility is
currently available from Texas Instruments.
NOTE:
Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily avoided with proper software configuration.
Table 23. Terminal Characteristics and Multiplexing
GZG
BALL
GDY
BALL
SIGNAL NAME
TYPE
MUX CTRL
SETTING
DESELECTED
INPUT STATE
PU/
PD
§
BUFFER
STRENGTH
OTHER
RESET
STATE#
SUPPLY
C3
A1
SDRAM.WE
O/Z
NA
NA
4 mA
A
1
DVDD4
DVDD4
DVDD4
DVDD4
DVDD4
A2
C4
SDRAM.RAS
O/Z
NA
NA
4 mA
A
1
D4
A2
SDRAM.DQMU
O/Z
NA
NA
4 mA
A
1
B3
B2
SDRAM.DQML
O/Z
NA
NA
4 mA
A
1
D5
C4
B4
D6
C5
H8
C6
B6
D7
C7
D8
B8
G8
C8
G9
B9
D4
C5
G8
B4
B5
C6
A3
E6
D6
A4
B6
F7
C7
B7
E7
A6
SDRAM.D[15:0]
I/O/Z
NA
NA
4 mA
E
0
D9
D7
SDRAM.CKE
O/Z
NA
NA
4 mA
A
1
DVDD4
DVDD4
DVDD4
DVDD4
C9
A7
SDRAM.CLK
I/O/Z
NA
NA
8 mA
E
LZ
H9
F8
SDRAM.CAS
O/Z
NA
NA
4 mA
A
1
D10
C10
C9
B8
SDRAM.BA[1:0]
O/Z
NA
NA
4 mA
A
0
G10
H10
C11
D11
G11
C12
D12
H11
C13
D13
G12
C14
B14
C8
B9
E9
A8
C10
F9
D9
A9
D10
C11
B10
A10
B11
SDRAM.A[12:0]
O/Z
NA
NA
4 mA
A
0
DVDD4
D14
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
§PD20 = 20-
μ
A internal pulldown, PD100 = 100-
μ
A pulldown, PU20 = 20-
μ
A internal pullup, PU100 = 100-
μ
A internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
D = I2C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
|| UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
D11
LCD.VS
O
NA
NA
4 mA
J, A, G1
0
DVDD1
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
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