參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 48/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Functional Overview
36
August 2002 Revised August 2003
SPRS197B
3.2
MPU Memory Maps
3.2.1 MPU Global Memory Map
The MPU has a unified address space. Therefore, the internal and external memories for program and data
as well as peripheral registers and configuration registers are all accessed within the same address space.
The MPU space is always addressed using byte addressing. Table 31 provides a high level illustration of
the entire MPU addressable space. Further detail regarding the peripheral and configuration registers is
provided in Sections 3.2.2, 3.15, and 3.17.
Table 31. OMAP5910 MPU Global Memory Map
BYTE ADDRESS RANGE
ON-CHIP
EXTERNAL INTERFACE
0x0000 0000 0x01FF FFFF
EMIFS (Flash CS0)
32M bytes
0x0200 0000 0x03FF FFFF
Reserved
0x0400 0000 0x05FF FFFF
EMIFS (Flash CS1)
32M bytes
0x0600 0000 0x07FF FFFF
Reserved
0x0800 0000 0x09FF FFFF
EMIFS (Flash CS2)
32M bytes
0x0A00 0000 0x0BFF FFFF
Reserved
0x0C00 0000 0x0DFF FFFF
EMIFS (Flash CS3)
32M bytes
0x0E00 0000 0x0FFF FFFF
Reserved
0x1000 0000 0x13FF FFFF
EMIFF (SDRAM)
64M bytes
0x1400 0000 0x1FFF FFFF
Reserved
0x2000 0000 0x2002 FFFF
IMIF Internal SRAM
192K bytes
0x2003 0000 0x2FFF FFFF
Reserved
0x3000 0000 0x5FFF FFFF
Local Bus space for USB Host
0x6000 0000 0xDFFF FFFF
Reserved
0xE000 0000 0xE0FF FFFF
DSP public memory space
(accessible via MPUI)
16M bytes
0xE100 0000 0xEFFF FFFF
DSP public peripherals
(accessible via MPUI)
0xF000 0000 0xFFFA FFFF
Reserved
0xFFFB 0000 0xFFFB FFFF
MPU public peripherals
0xFFFC 0000 0xFFFC FFFF
MPU/DSP shared peripherals
0xFFFD 0000 0xFFFE FFFF
MPU private peripherals
0xFFFF 0000 0xFFFF FFFF
Reserved
Some peripherals within this memory region are actually shared peripherals (UART 1,2,3).
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