參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 109/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Functional Overview
97
August 2002 Revised August 2003
SPRS197B
Table 370. UART3/IrDA Registers
DSP WORD
ADDRESS
MPU BYTE
ADDRESS
MPU BYTE
ADDRESS
(VIA MPUI)
REGISTER
NAME
DESCRIPTION
ACCESS
WIDTH
ACCESS
TYPE
RESET
VALUE
0x00 CC00h
FFFB:9800
E101:9800
UART3_RHR
UART3_THR
UART3_DLL§
UART3_IER
UART3_DLH§
UART3 receive holding register
8
R
Undefined
0x00 CC00h
FFFB:9800
E101:9800
UART3 transmit holding register
8
W
Undefined
0x00 CC00h
FFFB:9800
E101:9800
UART3 divisor latch low register
8
RW
00h
0x00 CC01h
FFFB:9804
E101:9802
UART3 interrupt enable register
8
RW
00h
0x00 CC01h
FFFB:9804
E101:9802
UART3 divisor latch high register
8
RW
00h
0x00 CC02h
FFFB:9808
E101:9804
UART3_IIR
UART3 interrupt identification
register
8
R
01h
0x00 CC02h
FFFB:9808
E101:9804
UART3_FCR
UART3_EFR§
UART3 FIFO control register
8
W
00h
0x00 CC02h
FFFB:9808
E101:9804
UART3 enhanced feature register
8
RW
00h
0x00 CC03h
FFFB:980C
E101:9806
UART3_LCR
UART3_MCR
UART3_XON1§
UART3_LSR
UART3_XON2§
UART3_MSR
UART3 line control register
8
RW
00h
0x00 CC04h
FFFB:9810
E101:9808
UART3 modem control register
8
RW
00h
0x00 CC04h
FFFB:9810
E101:9808
UART3 XON1 register
8
RW
00h
0x00 CC05h
FFFB:9814
E101:980A
UART3 mode register
8
R
60h
0x00 CC05h
FFFB:9814
E101:980A
UART3 XON2 register
8
RW
00h
0x00 CC06h
FFFB:9818
E101:980C
UART3 modem status register
8
R
Undefined
0x00 CC06h
FFFB:9818
E101:980C
UART3_TCR#
UART3 transmission control
register
8
RW
0Fh
0x00 CC06h
FFFB:9818
E101:980C
UART3_XOFF1§
UART3_SPR
UART3_TLR#
UART3_XOFF2§
UART3 XOFF1 register
8
RW
00h
0x00 CC07h
FFFB:981C
E101:980E
UART3 scratchpad register
8
RW
00h
0x00 CC07h
FFFB:981C
E101:980E
UART3 trigger level register
8
RW
00h
0x00 CC07h
FFFB:981C
E101:980E
UART3 XOFF2 register
8
RW
00h
0x00 CC08h
FFFB:9820
E101:9810
UART3_MDR1
UART3 mode definition 1 register
8
RW
07h
0x00 CC09h
FFFB:9824
E101:9812
UART3_MDR2
UART3 mode definition register 2
8
RW
00h
0x00 CC0Ah
FFFB:9828
E101:9814
UART3_SFLSR
UART3 status FIFO line status
register
8
R
00h
0x00 CC0Ah
FFFB:9828
E101:9814
UART3_TXFLL
UART3 transmit frame length low
8
W
00h
0x00 CC0Bh
FFFB:982C
E101:9816
UART3_RESUME
UART3 resume register
8
R
00h
0x00 CC0Bh
FFFB:982C
E101:9816
UART3_TXFLH
UART3 transmit frame length high
8
W
00h
0x00 CC0Ch
FFFB:9830
E101:9818
UART3_SFREGL
UART3 status FIFO low register
8
R
Undefined
0x00 CC0Ch
FFFB:9830
E101:9818
UART3_RXFLL
UART3 receive frame length low
8
W
00h
0x00 CC0Dh
FFFB:9834
E101:981A
UART3_SFREGH
UART3 status FIFO high register
8
R
Undefined
0x00 CC0Dh
FFFB:9834
E101:981A
UART3_RXFLH
UART3_BLR
UART3_ACREG
UART3_DIV16§
UART3 receive frame length high
8
W
00h
0x00 CC0Eh
FFFB:9838
E101:981C
UART3 BOF control register
8
RW
40h
0x00 CC0Fh
FFFB:983C
E101:981E
UART3 auxiliary control register
8
RW
00h
0x00 CC0Fh
FFFB:983C
E101:981E
UART3 divide 1.6 register
8
RW
00h
0x00 CC10h
FFFB:9840
E101:9820
UART3_SCR
UART3 supplementary control
register
8
RW
00h
Register is accessible when LCR[7] = 0 (normal operating mode)
Register is accessible when LCR[7] = 1 and LCR[7:0]
§Register is accessible when LCR[7] = 0BFh
Register is write accessible when EFR[4] = 1
#Register is accessible when EFR[4] = 1 and MCR[6] = 1
0BFh
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