參數(shù)資料
型號： MX98905B
廠商： Macronix International Co., Ltd.
英文描述： IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口)
中文描述： IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線接口（IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線接口）
文件頁數(shù)： 81/86頁
文件大小： 352K
代理商： MX98905B
81
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTRISTICS
(Continued)
SYMBOL
PARAMETER
8 BIT
16 BIT
UNIT
MIN.
MAX.
MIN.
MAX.
T33
MSWR1deasserted to MSMD0-15
20
20
ns
invalid (Note 3)
T34
MEMA1-15 valid before /MSWRL
20
20
ns
asserted
T35
RCSXL or /BPCSL asserted to CHRDY
15
15
ns
asserted (Note 11)
T36
MSRDL, MSWRL asserted to CHRDY
0
0
ns
asserted
T37
MEMA1-15 valid to CHRDY asserted
15
15
ns
T38a
Driving data from SD0-15 on to
60
60
ns
MEMD0-15 to CHRDY asserted for
RAM access
T38b
Driving data from SD0-15 to CHRDY
260
260
ns
asserted for Boot PROM access
Note 1:
M16L, IO16 are only asserted for 16-bit transfers.
Note 2:
CHRDY is only deasserted if the NIC core cannot service the access immediately. It is held deasserted until the NIC core is ready,
causing the system to insert wait states.
Note 3:
On 8-bit trnasfers only 8 bits of MEHD0-15 and D0-7 are driven.
Note 4:
This is the earty CHRDY timing required by some machines, where CHRDY is referenced to BALE. In this mode of operation, under
certain circumstances, CHRDY will be asserted for cycles which are not for this device i.e., memory cycles or I/O cycles where SA0-9
match our address before reaching their valid state. In such a case the time to assert CHRDY, from MRDL, MWRL or SA0-9 invalid,
will be the same as the deassertion time specified.
Note 5:
This is the standard CHRDY timing where CHRDY is asserted after IORDL or IOWRL.
Note 6
: Read data valid is referenced to CHRDY when wait states have been inserted.
Note 7:
If no wait states are inserted read data valid can be measured from IORDL.
Note 8:
This is a minimum timing with no additional wait states.
Note 9:
This is the standard I/O 16 timing where /IO16 is asserted after a valid address decode and IORDL or IOWRL going active.
Note 10:
This is the late IO16L timing, required by some machines. Where IO16L is asserted after a valid address decode and IORDL or
IOWRL going active.
Note 11:
BPCS is asserted for a boot PROM access. RCSL for a RAM access. RCSXL refers to RCS1L and RCS2L Depending on the mode
of operation either or both can be asserted. See the Functional Bus Timing section for further explanation.
Note 12:
Specifications which measure delays from an active state to a high impedance state are not guaranteed by production test, but are
characterized and correlated to determine true driver turn-off time by simulating inherent R-C delay times. In test measurements.
相關(guān)PDF資料
PDF描述
MX98905BFC The MX98905 is designed for easy implementation of CSMA/CD local area networks,
MXA2312A Low Cost, +2,-2 g Dual Axis Accelerometer with Analog Outputs
MXA2500K Ultra Low Cost, 【1.0 g Dual Axis Accelerometer with Absolute Outputs
MXA2500KV Ultra Low Cost, 【1.0 g Dual Axis Accelerometer with Absolute Outputs
MXA6500G Low Cost, Low Noise 【1 g Dual Axis Accelerometer with Absolute Analog Outputs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MX98905BFC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The MX98905 is designed for easy implementation of CSMA/CD local area networks,
MX98L715BEC 制造商:MCNIX 制造商全稱:Macronix International 功能描述:3.3V SINGLE CHIP FAST ETHERNET NIC CONTROLLER
MX-9C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX
MX-9G 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX
MX9G100B 制造商:Panasonic Industrial Company 功能描述:90x90 gearhead for 40W motor,100:1
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*