參數(shù)資料
型號： MX98905B
廠商： Macronix International Co., Ltd.
英文描述： IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口)
中文描述： IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線接口（IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線接口）
文件頁數(shù)： 36/86頁
文件大?。?/td> 352K
代理商： MX98905B
36
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
SYMBOL
HCFRE
BIT
D0
DESCRIPTION
Register HCFRE Enable. Power on low.
0 : Disable HCFR.
1 : Enable HCFR. When user issues EESTORE in Configuration Register B,
contents in figh byte of OFH of EEPROM. Whcih is reserved at
New Page Enable/Page Select. Power on low.
0X: Normal Mode. User can access controller's internal registers.
10 : User can access IDPROM through IOBASE + 00..OFH in I/O map. See
table 4 for your reference.
11: New Page 1 selectsd. User can access HCMR, CC, ASR and
SIGNATURE. See "New Page 1 address assignment for I/O map" and "New
Page 1 address assignment for Memory map " for more detail information.
Make sure set NPGEN to 0 before normal operation. Data port and Reset port
in I/O map are accessible no matter what the value of NPGEN and PGSEL
are.
Auto Jump to Next I/O base. Power on low.
0 : Write a 0 to this bit has no effect.1 : Write an 1 to this bit will cause I/O base
auto jump follow the sequence described in section 9.5- - Auto Configuration.
In multiple LAN cards auto configuration's application (see section 9.5), if SID
hits the HID, then write an 1 to this bit has no effect. The first time writing an
1 to AUTO will cause IO base change to 300H no matter what the current IO
base is.
Whenever AUTO is issued, the value of IOAD2..0 in CA and PAGE in HCFR
will be updated automatically by the state machine inside the MX98905.
Either 7 or 15 IO bases should be determined before AUTO is issued to
prevent the internal state machine getting confused. Any IORDL signal
activates will reset this bit.
IDPROM Write Command. Power on low.
0 : Write a 0 to this bit has no effect.
1 : The MX98905 will write the first 4 words of PROM data (Net work I.D.,
Boardtype and Checksum) back to EEPROM when this bit is set. When the
operation is completed, this bit will be reset by MX98905 itself. Don't write
an 1 to this bit and EESTORE of CB simultaneously, this will cause internal
state machine malfunction.
Write CA, CB, CC, HCFR, The entire PROM content back to EEPROM.
Power on low.
0 : Only CA, CB, CC and HCFR are written back to EEPROM when
EESTORE bit of CB is set to 1.
1 : CA, CB, CC, HCFR, and the entire PROM content will be writtenback to
EEPROM when EESTORE bit is set to 1. If new Network I.D. is necessary,
make sure I.D. is updated before this bit–is set and before EESTORE bit is
set to1, the following write sequence will be followed after EESTORE bit is set
to 1,
CA, CB -> CC, HCFR -> IDO, IDI -> ID2, ID3 -> ID4, ID5 -> and the rest of the
content in PROM.
NPGEN,PGSEL
D2,D1
AUTO
D3
IDWCMD
D4
ALLWR
D5
HIDDEN COMMAND REGISTER (R/W) (HCMR)
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