參數(shù)資料
型號: MX98905B
廠商: Macronix International Co., Ltd.
英文描述: IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口)
中文描述: IEEE 802.3標(biāo)準(zhǔn),10BASE5,10Base2的控制器和集成總線接口(IEEE 802.3標(biāo)準(zhǔn),10BASE5,10Base2的控制器和集成總線接口)
文件頁數(shù): 50/86頁
文件大小: 352K
代理商: MX98905B
50
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
5. COMMAND REGISTERS (Continued)
SYMBOL
BIT
DESCRIPTION
STP
D0
STOP
: Software reset command, takes the controller offline; no Packets will be
received or transmitted if this bit is set high.
Any reception or transmission in progress will enter the reset state after operation is
completed. This bit must be cleared and the STA bit must be set high to exit the reset
state. The software reset is executed only when the RST bit in the ISR is set to 1. STP
powers up high.
Note: If the ENC has previously been in start mode and the STP is set, both the STP
and STA bits will remain set.
STA
D1
START
: This bit is used to activate the ENC after either power-up, or when the ENC
has been placed in a reset mode by software command or error. STA powers up low.
TXP
D2
TRANSMIT PACKET
: This bit must be set to initiate transmission of a packet only
after the Transmit Byte Count (TBCR1 and TBCR0) and Transmit Page Start register
(TPSR) have been programmed. TXP is internally reset either after the transmission
is completed or aborted.
PD0, PD1,
PD2
D3, D4, D5
REMOTE DMA COMMAND
: These three-encoded bits control operation of the
Remote DMA channel. RD2 can be set to abort any Remote DMA command in
progress. The Remote Byte Count Registers should be cleared by host whenever a
Remote DMA has been aborted. The Remote Start Addresses are not restored to the
starting address if the Remote DMA is aborted. Hence, for another remote DMA
operaton, host should provide a starting address for ENC in order to operate
correctly.
RD2
0
0
0
0
1
RD1
0
0
1
1
X
RD0
0
1
0
1
X
Not Allowed
Remote Read
Remote Write
Send Packet
Abort/Complete Remote DMA (Note)
PS0, PS1
D6, D7
PAGE SELECT
: These two-encoded bits select which register page is to be
accessed with addresses RA0-3
PS1
0
0
1
1
PS0
0
1
0
1
Register Page 0
Register Page 1
Register Page 2
Reserved
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