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參數(shù)資料
| 型號(hào)： | MX98905B |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口) |
| 中文描述： | IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線接口（IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線接口） |
| 文件頁(yè)數(shù)： | 42/86頁(yè) |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905B |
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42
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
3.2 CONFIGURATION REGISTER B (R/W) (CB)
This register can be accessed by reading 0BH of
internal page 0 register followed by writing to that
address. If other Read/Write takes place between the
read and the write, then write to 0BH will access the
Remote Byte Count Register 1. When loading from
EEPROM during power-on reset, note that the value of
EESTORE is always 0, i.e., the value of EESTORE can
only be changed during Register Write operation.
PHYS0
PHYS1
GDLINK
IO16CON
CHANRDY
BE
BPWR
EESTRORE
0
1
2
3
4
5
6
7
Bits
SYMBOL
BIT
DESCRIPTION
PHYS0-1
D0-D1
PHYSICAL LAYER INTERFACE.
PHYS1
0
0
1
1
PHYS0
0
1
0
1
INTERFADCE
TPI (10BASE-T compatible Squelch Level)
Thin Ethernet (10BASE2, THIN pin high)
Thick Ethernet (10BASE5, AUI port)
TPI (Reduced Squelch Level)
The THIN pin can be used to enable the DC-DC converter required by 10BASE2
specification to provide electrical isolation.
GDLINK
D2
GOOD LINK.
There are different definitions for this bit in Write and Read modes.
Write Mode : Write 1 to this bit will disable the link pulse integrity test.
Read Mode : When this bit is read, it indicates the link status, reflecting the value
shown on the GDLINKL LED.
0 :
A. The MX98905 is in AUI mode
B. The MX98905 is in TPI mode, link enable, link bad
A. Link disable
B. The MX98905 is in TPI mode, link enable, link good
1 :
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