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| 型號： | MX98905B |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口) |
| 中文描述： | IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線接口（IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線接口） |
| 文件頁數(shù)： | 26/86頁 |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905B |
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26
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
14. JABBER
Whenever the transmitter is active for greater than
52 ms, the jabber timer monitors the transmitter and
disables the transmission. In this case, the
transmitter is then disabled for the time that ENDEC
module’s internal transmit enable is asserted. This
signal has to be deasserted for about 750 ms before
the jabber re-enables the transmit outputs.
15. TRANSMIT DRIVER
The transmitter has four signals, the true and com-
plement Manchester-encoded data (TXOP and
TXOM). These signals may be delayed by 50 ns
(TXODP and TXODM).
These four signals are combined, TXOP with
TXODM and TXOM with TXODP. Known as digital
pre-emphasis, this process is required to
compensate for the twisted-pair cable which acts
like a low-pass filter and can greatly weaken the 10
MHz (50 ns) pulses of the Manchester-encoded
waveform than the 5 MHz (100 ns) pulses.
A combination of these signals is shown below:
DATA
PATTERN
1
1
0
0
1
1
TXOP
TXODM
COMBINED
WAVEFORM
WITH
PRE-EMPHASIS
seven consecutive link pulses or three consecutive link
pulses having reversed polarity are detected. A wiring
error at either end of the TPI cable can cause polarity
reversal. Upon detection of this reversal the condition
is latched and POL is asserted. Correcting this error is
the TP1 and will also decode received data correctly,
thus getting rid of the need to check the wiring error.
17. MANCHESTER ENCODER AND DIFFERENTIAL
DRIVER
On the transformer’s secondary, the differential trans-
mit pair drives up to 50 meters of twisted-pair AUI
cable. These outputs are source followers requiring
two 270
W
pulldown resistors to ground.
18. MANCHESTER DECODER
This decoder is composed of a differential receiver and
a PLL to separate a Manchester-decoded data stream
into internal clocks signals and data. When using the
standard 78
W
transceiver drop cable, see that the dif-
ferential input must be externally terminated with two
39
W
resistors connected in series. These resistors are
optional in Thin Ethernet applications. A squelch
circuit at the input rejects signals with levels less than -
175 mV to prevent noise from triggering the decoder.
And signals negative than -300 mV are decoded; data
becomes valid within 5 bit times. The MX98905 may
be able to take bit jitter up to 18 ns in the data that is
received.
19. COLLISION TRANSLATOR
If the Ethernet transceiver, when in AUI mode, detects
a collision, it generates a 10 MHz signal to the differen-
tial collision inputs (CDP and CDM) of the MX98905.
When these inputs are active, the MX98905 uses this
signal to cancel its current transmission and resched-
ule another one.
The collision differential inputs are ended in the same
way as the differential receive inputs. The squelch
circuitry is also similar, rejecting pulses with levels less
than -175 mV.
20. RECEIVE DESERIALIZER
The receive deserializer starts to work when the input
16. STATUS INFORMATION
This information is shown at the ENC on the CRS/RX,
TXE/TX, COL and POL outputs as decribed in the pin
description table. These outputs can drive status LEDs
by means of an appropriate driver circuit.
Normally low, the POL output will be driven high when
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