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參數(shù)資料
| 型號(hào)： | MX98905B |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線(xiàn)接口) |
| 中文描述： | IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線(xiàn)接口（IEEE 802.3標(biāo)準(zhǔn)，10BASE5，10Base2的控制器和集成總線(xiàn)接口） |
| 文件頁(yè)數(shù)： | 51/86頁(yè) |
| 文件大小： | 352K |
| 代理商： | MX98905B |
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51
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
6. INTERRUPT STATUS REGISTER (ISR) 07H
(READ/WRITE)
This register is accessed by the host processor to de-
termine the cause of an interrupt. Any interrupt can be
masked in the Interrupt Mask Register (IMR). Individ-
ual interrupt bits are cleared by writing a "1" into the
corresponding bit of the ISR. The INT signal is active
as long as any unmasked signal is set; it will not go low
until all unmasked bits in this register have been
cleared. The ISR must be cleared after power-up by
writing it with all 1's.
PRX
PTX
RXE
TXE
OVW
CNT
RDC
RST
0
1
2
3
4
5
6
7
Bits
SYMBOL
BIT
DESCRIPTION
PRX
D0
PACKET RECEIVED
: Indicates packet received with no errors.
PTX
D1
PACKET TRANSMITTED
: Indicates packet transmitted with no errors.
RXE
D2
RECEIVE ERROR
: Indicates that a packet was received with one or more of the
following errors:
- CRC Error
- Frame Alignment Error
- FIFO Overrun
- Missed Packet
TXE
D3
TRANSMIT ERROR
: Set when packet is transmitted with one or more of the following
errors:
- Excessive Collisions
- FIFO Underrun
OVW
D4
OVERWRITE WARNING:
Set when receive buffer ring storage resources have been
exhausted. (Current Pointer has reached Boundary Pointer)
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