參數(shù)資料
型號(hào): MX98742
英文描述: FEBC 100 Base Fast Ethernet Bridge Controller
中文描述: FEBC 100基地快速以太網(wǎng)橋控制器
文件頁數(shù): 9/36頁
文件大小: 166K
代理商: MX98742
9
MX98745
P/N:PM0427
REV. 1.4, JUL. 8, 1998
F. LED Display (Continued)
PAD #
83
Name
LED2/
TXMII
I/O
I/O,
TTL
Description
LED 2/Port0 TX/MII mode Select. When Power on reset, value on this pin
will be latched at the rising edge of RESETL and be the value of TXMII which
can program the universal port (port 0) to TX mode (5B interface) or MII mode
(4B) interface. When TXMII is set to 1, Port 0 of XRC II will be programmed to
TX mode and PMSEL will be disabled. In normal operation (after power on
reset), this pin will display port 2's Receivee/Link, Partition, Isolation status
and indicates 30% Network utilization and 9% collision rate according to the
value on LDS[2:0]
LED 3/Physical Address 0. Value on LED3 will be latched at the rising edge of
RESET as the setting of Device physical address 0. If EECONF is set to 1,
PHY0 will be overwritten by the contents of EEPROM.
After EEPROM operation is completed (in case EECONF is set to 1), this pin
will display port 3's Receivee/Link, Partition, Isolation status and indicates 10%
Network utilization and 8% collision rate according to the value on LDS[2:0]
LED 4/Physical Address 1. Value on LED4 will be latched at the rising edge of
RESETL as the physical address 1 of MX98745. If EECONF is set, Physical
address will be overwritten by the value from EEPROM.
After EEPROM operation is completed, this pin will display port 4's Receivee/
Link, Partition, Isolation status and indicates 20% Network utilization and 10%
collision rate according to the value on LDS[2:0].
LED 5/Physical Address 2. Value on LED5 will be latched at the rising edge of
RESETL as the physical address 2 of MX98745. If EECONF is set, Physical
address will be overwritten by the value from EEPROM.
After EEPROM operation is completed, this pin will display port 5's Receivee/
Link, Partition, Isolation status and indicates 40% Network utilization and 13%
collision rate according to the value on LDS[2:0].
LED 6/Physical Address 3. Value on LED6 will be latched at the rising edge of
RESETL as the physical address 3 of MX98745. If EECONF is set, Physical
address will be overwritten by the value from EEPROM.
After EEPROM operation is completed, this pin will display port 6's Receivee/
Link, Partition, Isolation status and indicates 60% Network utilization and 15%
collision rate according to the value on LDS[2:0].
84
LED3/
PHY0
I/O,
TTL
85
LED4/
PHY1
I/O,
TTL
86
LED5/
PHY2
I/O,
TTL
87
LED6/
PHY3
I/O,
TTL
Table 5-1 Pin Description for XRC II (Continued)
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