參數(shù)資料
型號: MX98742
英文描述: FEBC 100 Base Fast Ethernet Bridge Controller
中文描述: FEBC 100基地快速以太網(wǎng)橋控制器
文件頁數(shù): 21/36頁
文件大小: 166K
代理商: MX98742
21
MX98745
P/N:PM0427
REV. 1.4, JUL. 8, 1998
J. Elastic Buffer Over/Underflow Status Register (register #27) (R)
Bit(s)
27.15:0
27.7
Name
Reserved
EBOUF7
Description
Always 0.
1 : Elastic Buffer Over/Underflow at Port 7
0 : Normal Condition.
Clear to 0 after read.
1 : Elastic Buffer Over/Underflow at Port 6
0 : Normal Condition.
Clear to 0 after read.
1 : Elastic Buffer Over/Underflow at Port 5
0 : Normal Condition.
Clear to 0 after read.
1 : Elastic Buffer Over/Underflow at Port 4
0 : Normal Condition.
Clear to 0 after read.
1 : Elastic Buffer Over/Underflow at Port 3
0 : Normal Condition.
Clear to 0 after read.
1 : Elastic Buffer Over/Underflow at Port 2
0 : Normal Condition.
Clear to 0 after read.
1 : Elastic Buffer Over/Underflow at Port 1
0 : Normal Condition.
Clear to 0 after read.
1 : Elastic Buffer Over/Underflow at Port 0
0 : Normal Condition.
Clear to 0 after read.
R/W
R
R
27.6
EBOUF6
R
27.5
EBOUF5
R
27.4
EBOUF4
R
27.3
EBOUF3
R
27.2
EBOUF2
R
27.1
EBOUF1
R
27.0
EBOUF0
R
Table 6-10 Elastic Buffer Over/Underflow Status Register Bit Definition
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